AT91SAM7S32-AU-001 Atmel, AT91SAM7S32-AU-001 Datasheet - Page 725

IC ARM7 MCU 32BIT 32K 48LQFP

AT91SAM7S32-AU-001

Manufacturer Part Number
AT91SAM7S32-AU-001
Description
IC ARM7 MCU 32BIT 32K 48LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91SAM7S32-AU-001

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
I²C, SPI, SSC, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
For Use With
AT91SAM7S-EK - KIT EVAL FOR ARM AT91SAM7S
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
AT91SAM7S32-AU001

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT91SAM7S32-AU-001
Manufacturer:
Atmel
Quantity:
10 000
Company:
Part Number:
AT91SAM7S32-AU-001
Quantity:
2 100
40.19.8.3
40.19.9
40.19.9.1
40.19.9.2
40.19.9.3
6175K–ATARM–30-Aug-10
Two-wire Interface (TWI)
SSC: Transmitter Limitations in Slave Mode
TWI: Clock Divider
TWI: Software Reset
TWI: Disabling Does not Operate Correctly
If TK is programmed as an input and TF is programmed as an output and requested to be set to
low/high during data emission, the Frame Synchro signal is generated one bit clock period after
the data start and one data bit is lost. This problem does not exist when generating a periodic
synchro.
The data need to be delayed for one bit clock period with an external assembly.
In the following schematic, TD, TK and NRST are AT91SAM7S signals, TXD is the delayed data
to connect to the device.
The value of CLDIV x 2
be less than or equal to 8191⋅
None.
When a software reset is performed during a frame and when TWCK is low, it is impossible to
initiate a new transfer in READ or WRITE mode.
None.
Any transfer in progress is immediately frozen if the Control Register (TWI_CR) is written with
the bit MSDIS at 1. Furthermore, the status bits TXCOMP and TXRDY in the Status Register
(TWI_SR) are not reset.
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
CKDIV
must be less than or equal to 8191, the value of CHDIV x 2
AT91SAM7S Series Preliminary
CKDIV
must
725

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