AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 105

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

15. WD: Watchdog Timer
15.1
6174B–ATARM–07-Nov-05
Block Diagram
The AT91FR40162S has an internal watchdog timer which can be used to prevent system lock-
up if the software becomes trapped in a deadlock. In normal operation the user reloads the
watchdog at regular intervals before the timer overflow occurs. If an overflow does occur, the
watchdog timer generates one or a combination of the following signals, depending on the
parameters in WD_OMR (Overflow Mode Register):
The watchdog timer has a 16-bit down counter. Bits 12-15 of the value loaded when the watch-
dog is restarted are programmable using the HPVC parameter in WD_CMR (Clock Mode). Four
clock sources are available to the watchdog counter: MCK/8, MCK/32, MCK/128 or MCK/1024.
The selection is made using the WDCLKS parameter in WD_CMR. This provides a programma-
ble time-out period of 1 ms to 2 sec. with a 33 MHz system clock.
All write accesses are protected by control access keys to help prevent corruption of the watch-
dog should an error condition occur. To update the contents of the mode and control registers it
is necessary to write the correct bit pattern to the control access key bits at the same time as the
control bits are written (the same write access).
Figure 15-1. Watchdog Timer Block Diagram
• If RSTEN is set, an internal reset is generated (WD_RESET as shown in
• If IRQEN is set, a pulse is generated on the signal WDIRQ which is connected to the
• If EXTEN is set, a low level is driven on the NWDOVF signal for a duration of 8 MCK cycles.
MCKI/1024
MCKI/128
Advanced Interrupt Controller
MCKI/32
MCKI/8
WD_RESET
Advanced
Bus (APB)
Peripheral
WDIRQ
Clock Select
AT91FR40162S Preliminary
Control Logic
CLK_CNT
Clear
Overflow
Programmable
Down Counter
16-bit
Figure
15-1).
NWDOVF
105