AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 122

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

17.5
17.5.1
17.5.2
122
Transmitter
AT91FR40162S Preliminary
Time-guard
Multi-drop Mode
The transmitter has the same behavior in both synchronous and asynchronous operating
modes. Start bit, data bits, parity bit and stop bits are serially shifted, lowest significant bit first,
on the falling edge of the serial clock. See example in Figure 17-6.
The number of data bits is selected in the CHRL field in US_MR.
The parity bit is set according to the PAR field in US_MR.
The number of stop bits is selected in the NBSTOP field in US_MR.
When a character is written to US_THR (Transmit Holding), it is transferred to the Shift Register
as soon as it is empty. When the transfer occurs, the TXRDY bit in US_CSR is set until a new
character is written to US_THR. If Transmit Shift Register and US_THR are both empty, the
TXEMPTY bit in US_CSR is set.
The Time-guard function allows the transmitter to insert an idle state on the TXD line between
two characters. The duration of the idle state is programmed in US_TTGR (Transmitter Time-
guard). When this register is set to zero, no time-guard is generated. Otherwise, the transmitter
holds a high level on TXD after each transmitted byte during the number of bit periods pro-
grammed in US_TTGR
When the field PAR in US_MR equals 11X (binary value), the USART is configured to run in
Multi-drop Mode. In this case, the parity error bit PARE in US_CSR is set when data is detected
with a parity bit set to identify an address byte. PARE is cleared with the Reset Status Bits Com-
mand (RSTSTA) in US_CR. If the parity bit is detected low, identifying a data byte, PARE is not
set.
The transmitter sends an address byte (parity bit set) when a Send Address Command
(SENDA) is written to US_CR. In this case, the next byte written to US_THR will be transmitted
as an address. After this any byte transmitted will have the parity bit cleared.
Figure 17-6. Synchronous and Asynchronous Modes: Character Transmission
Baud Rate
Example: 8-bit, parity enabled 1 stop
Clock
TXD
between two characters
Start
Bit
Idle state duration
D0
D1
D2
=
D3
Time-guard
D4
Value
D5
x
D6
Period
Bit
D7
6174B–ATARM–07-Nov-05
Parity
Bit
Stop
Bit