AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 148
AT91FR40162S-CJ
Manufacturer Part Number
AT91FR40162S-CJ
Description
IC ARM MCU FLASH 1K 121BGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91FR40162S-CJ.pdf
(210 pages)
Specifications of AT91FR40162S-CJ
Core Processor
ARM7
Core Size
16/32-Bit
Speed
75MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
WDT
Number Of I /o
32
Program Memory Size
2MB (1M x 16)
Program Memory Type
FLASH
Ram Size
256K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
121-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT91FR40162S-CJ
Manufacturer:
ATMEL
Quantity:
455
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18.2
Table 18-1.
Note:
18.3
18.3.1
148
Signal Description
After a hardware reset, the Timer Counter block pins are controlled by the PIO Controller. They must be configured to be con-
trolled by the peripheral before being used.
Timer Counter Description
TCLK0, TCLK1, TCLK2
AT91FR40162S Preliminary
Counter
Channel Signal
XC0, XC1, XC2
Block Signals
Signal Description
TIOA0
TIOB0
TIOA1
TIOB1
TIOA2
TIOB2
SYNC
TIOA
TIOB
INT
The three Timer Counter channels are independent and identical in operation. The registers for
channel programming are listed in
Each Timer Counter channel is organized around a 16-bit counter. The value of the counter is
incremented at each positive edge of the selected clock. When the counter has reached the
value 0xFFFF and passes to 0x0000, an overflow occurs and the bit COVFS in TC_SR (Status
Register) is set.
The current value of the counter is accessible in real-time by reading TC_CV. The counter can
be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of
the selected clock.
Description
External Clock Inputs
Capture Mode: General Purpose Input
Waveform Mode: General Purpose Output
Capture Mode: General Purpose Input
Waveform Mode: General Purpose Input/Output
Interrupt Signal Output
Synchronization Input Signal
Description
External Clock Inputs
TIOA Signal for Channel 0
TIOB Signal for Channel 0
TIOA Signal for Channel 1
TIOB Signal for Channel 1
TIOA Signal for Channel 2
TIOB Signal for Channel 2
Table 18-3 on page
157.
6174B–ATARM–07-Nov-05
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