AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 152

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

18.4
18.4.1
18.4.2
18.4.3
152
Capture Operating Mode
AT91FR40162S Preliminary
Capture Registers A and B (RA and RB)
Trigger Conditions
Status Register
This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register).
Capture Mode allows the TC Channel to perform measurements such as pulse timing, fre-
quency, period, duty cycle and phase on TIOA and TIOB signals which are inputs.
Figure shows the configuration of the TC Channel when programmed in Capture Mode.
Registers A and B are used as capture registers. This means that they can be loaded with the
counter value when a programmable event occurs on the signal TIOA.
The parameter LDRA in TC_CMR defines the TIOA edge for the loading of register A, and the
parameter LDRB defines the TIOA edge for the loading of Register B.
RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since
the last loading of RA.
RB is loaded only if RA has been loaded since the last trigger or the last loading of RB.
Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS)
in TC_SR (Status Register). In this case, the old value is overwritten.
In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trig-
ger can be defined.
Bit ABETRG in TC_CMR selects input signal TIOA or TIOB as an external trigger. Parameter
ETRGEDG defines the edge (rising, falling or both) detected to generate an external trigger. If
ETRGEDG = 0 (none), the external trigger is disabled.
The following bits in the status register are significant in Capture Operating Mode.
Note:
• CPCS: RC Compare Status
• COVFS: Counter Overflow Status
• LOVRS: Load Overrun Status
• LDRAS: Load RA Status
• LDRBS: Load RB Status
• ETRGS: External Trigger Status An external trigger on TIOA or TIOB has been detected
There has been an RC Compare match at least once since the last read of the status
The counter has attempted to count past $FFFF since the last read of the status
RA or RB has been loaded at least twice without any read of the corresponding register,
since the last read of the status
RA has been loaded at least once without any read, since the last read of the status
RB has been loaded at least once without any read, since the last read of the status
since the last read of the status
All the status bits are set when the corresponding event occurs and they are automatically cleared
when the Status Register is read.
6174B–ATARM–07-Nov-05