AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 12

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

12
AT91FR40162S Preliminary
The user must ensure that all VDDIO, VDDCORE and all GND pins are connected to their
respective supplies by the shortest route. The Flash memory powers-on in read mode. Com-
mand sequences are used to place the device in other operating modes, such as program and
erase.
A separate Flash memory reset input pin (NRSTF) is provided for maximum flexibility, enabling
the reset operation to adapt to the application. When this input is at a logic high level, the mem-
ory is in its standard operating mode; a low level on this input halts the current memory
operation and puts its outputs in a high impedance state.
The Flash memory features data polling to detect the end of a program cycle. While a program
cycle is in progress, an attempted read of the last word written will return the complement of the
written data on I/O7. An open-drain NBUSY output pin provides another method of detecting the
end of a program or erase cycle. This pin is pulled low while program and erase cycles are in
progress and is released at the completion of the cycle. A toggle bit feature provides a third
means of detecting the end of a program or erase cycle.
The Flash memory is divided into 39 sectors for erase operations. To further enhance device
flexibility, an Erase Suspend feature is offered. This feature puts the erase cycle on hold for an
indefinite period and allows the user to read data from, or to write data to, any other sector within
the same memory plane. There is no need to suspend an erase cycle if the data to be read is in
the other memory plane.
The device has the capability to protect data stored in any sector. Once the data protection for a
sector is enabled, the data in that sector cannot be changed while input levels lie between
ground and VDDIO.
Note: This data protection does not prevent read accesses of the Flash.
An optional VPP pin is available to enhance program/erase times.
A 6-byte command sequence (Enter Single Pulse Program Mode) allows the device to be written
to directly, using single pulses on the write control lines. This mode (Single-pulse Programming)
is exited by powering down the device or by pulsing the NRSTF pin low for a defined duration
and then bringing it back to VDDIO.
The following hardware features protect against inadvertent programming of the Flash memory:
• VDDIO Sense – if VDDIO is below a certain level, the program function is inhibited.
• VDDIO Power-on Delay – once VDDIO has reached the VDDIO sense level, the device will
• Program Inhibit – holding any one of OE low, CE high or WE high inhibits program cycles.
• Noise Filter – pulses of less than a certain duration on the WE or CE inputs will not initiate a
automatically time out a certain duration before programming.
program cycle.
6174B–ATARM–07-Nov-05