AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 91

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

14. PIO: Parallel I/O Controller
14.1
14.2
14.3
6174B–ATARM–07-Nov-05
Multiplexed I/O Lines
Output Selection
I/O Levels
The AT91FR40162S has 32 programmable I/O lines. Six pins are dedicated as general purpose
I/O pins (P16, P17, P18, P19, P23 and P24). Other I/O lines are multiplexed with an external sig-
nal of a peripheral to optimize the use of available package pins (see
The PIO controller also provides an internal interrupt signal to the Advanced Interrupt Controller.
Some I/O lines are multiplexed with an I/O signal of a peripheral. After reset, the pin is generally
controlled by the PIO Controller and is in Input Mode.
these pins are not controlled by the PIO Controller after reset.
When a peripheral signal is not used in an application, the corresponding pin can be used as a
parallel I/O. Each parallel I/O line is bi-directional, whether the peripheral defines the signal as
input or output.
Parallel I/O signals.
If a pin is multiplexed between the PIO Controller and a peripheral, the pin is controlled by the
registers PIO_PER (PIO Enable) and PIO_PDR (PIO Disable). The register PIO_PSR (PIO Sta-
tus) indicates whether the pin is controlled by the corresponding peripheral or by the PIO
Controller.
If a pin is a general-purpose parallel I/O pin (not multiplexed with a peripheral), PIO_PER and
PIO_PDR have no effect and PIO_PSR returns 1 for the bits corresponding to these pins.
When the PIO is selected, the peripheral input line is connected to zero.
The user can enable each individual I/O signal as an output with the registers PIO_OER (Output
Enable) and PIO_ODR (Output Disable). The output status of the I/O signals can be read in the
register PIO_OSR (Output Status). The direction defined has effect only if the pin is configured
to be controlled by the PIO Controller.
Each pin can be configured to be driven high or low. The level is defined in four different ways,
according to the following conditions.
If a pin is controlled by the PIO Controller and is defined as an output (see “Output Selection”
above), the level is programmed using the registers PIO_SODR (Set Output Data) and
PIO_CODR (Clear Output Data). In this case, the programmed value can be read in PIO_ODSR
(Output Data Status).
If a pin is controlled by the PIO Controller and is not defined as an output, the level is determined
by the external circuit.
If a pin is not controlled by the PIO Controller, the state of the pin is defined by the peripheral
(see peripheral datasheets).
In all cases, the level on the pin can be read in the register PIO_PDSR (Pin Data Status).
Figure 14-1 on page 93
shows the multiplexing of the peripheral signals with
AT91FR40162S Preliminary
Table 14-1 on page 94
Table 14-1 on page
indicates which of
94).
91