AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 20

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

10. EBI: External Bus Interface
10.1
20
External Memory Mapping
AT91FR40162S Preliminary
The EBI generates the signals that control the access to the external memory or peripheral
devices. The EBI is fully-programmable and can address up to 64M bytes. It has eight chip
selects and a 24-bit address bus, the upper four bits of which are multiplexed with a chip select.
The 16-bit data bus can be configured to interface with 8- or 16-bit external devices. Separate
read and write control signals allow for direct memory and peripheral interfacing.
The EBI supports different access protocols allowing single-clock cycle memory accesses.
The main features are:
Section 10.11 ”EBI User Interface”, on page 44
The memory map associates the internal 32-bit address space with the external 24-bit address
bus.
The memory map is defined by programming the base address and page size of the external
memories (see
EBI_CSR7). Note that A0 - A23 is only significant for 8-bit memory; A1 - A23 is used for 16-bit
memory.
If the physical memory device is smaller than the programmed page size, it wraps around and
appears to be repeated within the page. The EBI correctly handles any valid access to the mem-
ory device within the page (see
In the event of an access request to an address outside any programmed page, an Abort signal
is generated. Two types of Abort are possible: instruction prefetch abort and data abort. The cor-
responding exception vector addresses are respectively 0x0000000C and 0x00000010. It is up
to the system programmer to program the error handling routine to use in case of an Abort (see
the ARM7TDMI datasheet for further information).
If two chip selects are defined as having the same base address, an access to the overlapping
address space asserts both NCS lines. The Chip Select Register with the smaller number
defines the characteristics of the external access and the behavior of the control signals.
• External memory mapping
• Up to 8 chip select lines
• 8- or 16-bit data bus
• Byte write or byte select lines
• Remap of boot memory
• Two different read protocols
• Programmable wait state generation
• External wait request
• Programmable data float time
“EBI User Interface”
Figure 10-1 on page
and the
“EBI Chip Select Register”
describes the EBI User Interface.
21).
describing EBI_CSR0 to
6174B–ATARM–07-Nov-05