AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 119

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

17.3
Figure 17-2. Baud Rate Generator
6174B–ATARM–07-Nov-05
MCK/8
MCK
SCK
Baud Rate Generator
USCLKS [0]
0
1
USCLKS [1]
0
1
The Baud Rate Generator provides the bit period clock (the Baud Rate clock) to both the
Receiver and the Transmitter.
The Baud Rate Generator can select between external and internal clock sources. The external
clock source is SCK. The internal clock sources can be either the master clock (MCK) or the
master clock divided by 8 (MCK/8).
Note:
When the USART is programmed to operate in Asynchronous Mode (SYNC = 0 in the Mode
Register US_MR), the selected clock is divided by 16 times the value (CD) written in US_BRGR
(Baud Rate Generator Register). If US_BRGR is set to 0, the Baud Rate Clock is disabled.
When the USART is programmed to operate in Synchronous Mode (SYNC = 1) and the selected
clock is internal (USCLKS[1] = 0 in the Mode Register US_MR), the Baud Rate Clock is the
internal selected clock divided by the value written in US_BRGR. If US_BRGR is set to 0, the
Baud Rate Clock is disabled.
In Synchronous Mode with external clock selected (USCLKS[1] = 1), the clock is provided
directly by the signal on the SCK pin. No division is active. The value written in US_BRGR has
no effect.
Baud Rate
Baud Rate
In all cases, if an external clock is used, the duration of each of its levels must be longer than the
system clock (MCK) period. The external clock frequency must be at least 2.5 times lower than the
system clock.
CLK
16-bit Counter
=
=
CD
Selected Clock
Selected Clock
16 x CD
CD
USCLKS [1]
SYNC
OUT
0
CD
>1
1
0
AT91FR40162S Preliminary
0
1
Divide
by 16
SYNC
0
1
Baud Rate
Clock
119