AT91FR40162S-CJ Atmel, AT91FR40162S-CJ Datasheet - Page 79

• Manufacturer Part Number: AT91FR40162S-CJ
• Description: IC ARM MCU FLASH 1K 121BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91FR40162S-CJ

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 75MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: WDT
• Number Of I /o: 32
• Program Memory Size: 2MB (1M x 16)
• Program Memory Type: FLASH
• Ram Size: 256K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -

Table 13-2.
Notes:
13.11 Standard Interrupt Sequence
6174B–ATARM–07-Nov-05
Action
Calculate active interrupt (higher than current or spurious)
Determine and return the vector of the active interrupt
Memorize interrupt
Push on internal stack the current priority level
Acknowledge the interrupt
No effect
1. NIRQ de-assertion and automatic interrupt clearing if the source is programmed as level sensitive.
2. Software that has been written and debugged using Protect Mode will run correctly in Normal Mode without modification.
(2)
However, in Normal Mode the AIC_IVR write has no effect and can be removed to optimize the code.
Order of Interrupt Steps According to Mode
(1)
It is assumed that:
When NIRQ is asserted, if the bit I of CPSR is 0, the sequence is:
• The Advanced Interrupt Controller has been programmed, AIC_SVR are loaded with
• The Instruction at address 0x18(IRQ exception vector address) is
1. The CPSR is stored in SPSR_irq, the current value of the Program Counter is loaded in
2. The ARM core enters IRQ Mode, if it is not already.
3. When the instruction loaded at address 0x18 is executed, the Program Counter is
4. The previous step has effect to branch to the corresponding interrupt service routine.
5. Further interrupts can then be unmasked by clearing the I bit in the CPSR, allowing re-
6. The Interrupt Handler can then proceed as required, saving the registers which will be
corresponding interrupt service routine addresses and interrupts are enabled.
ldr pc, [pc, # - &F20]
the IRQ link register (r14_irq) and the Program Counter (r15) is loaded with 0x18. In the
following cycle during fetch at address 0x1C, the ARM core adjusts r14_irq, decrement-
ing it by 4.
loaded with the value read in AIC_IVR. Reading the AIC_IVR has the following effects:
– Set the current interrupt to be the pending one with the highest priority. The current
– De-assert the NIRQ line on the processor. (Even if vectoring is not used, AIC_IVR
– Automatically clear the interrupt, if it has been programmed to be edge triggered
– Push the current level on to the stack
– Return the value written in the AIC_SVR corresponding to the current interrupt
This should start by saving the Link Register(r14_irq) and the SPSR(SPSR_irq). Note
that the Link Register must be decremented by 4 when it is saved, if it is to be restored
directly into the Program Counter at the end of the interrupt.
assertion of the NIRQ to be taken into account by the core. This can occur if an inter-
rupt with a higher priority than the current one occurs.
used and restoring them at the end. During this phase, an interrupt of priority higher
than the current level will restart the sequence from step 1. Note that if the interrupt is
level is the priority level of the current interrupt.
must be read in order to de-assert NIRQ)
AT91FR40162S Preliminary
Read AIC_IVR
Read AIC_IVR
Read AIC_IVR
Read AIC_IVR
Read AIC_IVR
Write AIC_IVR
Normal Mode
Read AIC_IVR
Read AIC_IVR
Read AIC_IVR
Write AIC_IVR
Write AIC_IVR
Protect Mode
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