ATTINY15L-1SU Atmel, ATTINY15L-1SU Datasheet
ATTINY15L-1SU
Specifications of ATTINY15L-1SU
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ATTINY15L-1SU Summary of contents
Page 1
... Internal 1.6 MHz System Clock Pin Configuration PDIP/SOIC (RESET/ADC0) PB5 (ADC3) PB4 (ADC2) PB3 GND ® 8-bit Microcontroller 1 8 VCC 2 7 PB2 (ADC1/SCK/T0/INT0 PB1 (AIN1/MISO/OC1A PB0 (AIN0/AREF/MOSI) 8-bit Microcontroller with 1K Byte Flash ATtiny15L Not recommended for new design Rev. 1187H–AVR–09/07 1 ...
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... Power-saving modes. The device is manufactured using Atmel’s high-density, Non-volatile memory technol- ogy. By combining a RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny15L is a powerful microcontroller that provides a highly flexible and cost-efficient solution to many embedded control applications. The peripheral features make the ATtiny15L par- ticularly suited for battery chargers, lighting ballasts and all kinds of intelligent sensor applications ...
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... Block Diagram 1187H–AVR–09/07 Figure 1. The ATtiny15L Block Diagram VCC GND PROGRAM STACK COUNTER POINTER PROGRAM HARDWARE FLASH STACK INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS INSTRUCTION DECODER CONTROL ALU LINES STATUS REGISTER PROGRAMMING ISP MODULE LOGIC DATA REGISTER PORT B PORT B DRIVERS ...
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... There is an internal PLL that provides a 16x clock rate locked to the system clock (CK) for the use of the Peripheral Timer/Counter1. The nominal frequency of this peripheral clock, PCK, is 25.6 MHz. ATtiny15L 4 Port Pin Alternate Function ...
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... The ALU supports arithmetic and logic functions between registers or between a con- stant and a register. Single-register operations are also executed in the ALU. Figure 2 shows the ATtiny15L AVR RISC microcontroller architecture. The AVR uses a Harvard architecture concept with separate memories and buses for program and data memo- ries ...
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... Since all instructions are single 16-bit words, the Flash is organized as Memory 512 x 16 words. The Flash memory has an endurance of at least 1,000 write/erase cycles. The ATtiny15L Program Counter is nine bits wide, thus addressing the 512 words Flash Program memory. See page 54 for a detailed description on Flash memory programming. ATtiny15L ...
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... The ATtiny15L AVR RISC Microcontroller supports powerful and efficient addressing modes. This section describes the various addressing modes supported in the ATtiny15L. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. ...
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... Relative Program Addressing, Figure 8. Relative Program Memory Addressing RJMP and RCALL Program execution continues at address The relative address k is -2048 to 2047. Constant Addressing using Figure 9. Code Memory Constant Addressing the LPM Instruction ATtiny15L 8 +1 $1FF 1187H–AVR–09/07 ...
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... A4 followed by four subroutine or interrupt returns, will pop A4, A3, A2, and once more A2 from the Hardware Stack. The ATtiny15L contains 64 bytes of data EEPROM memory organized as a sepa- rate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on page 36, specifying the EEPROM Address Register, the EEPROM Data Register, and the EEPROM Control Register ...
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... Figure 11. Single Cycle ALU Operation I/O Memory The I/O space definition of the ATtiny15L is shown in Table 2. Table 2. ATtiny15L I/O Space ATtiny15L 10 T1 System Clock Ø Total Execution Time Register Operands Fetch ALU Operation Execute Result Write Back (1) Address Hex Name Function $3F SREG ...
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... Note: 1. Reserved and unused locations are not shown in the table. All ATtiny15L I/O and peripheral registers are placed in the I/O space. The I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions ...
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... The Carry Flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set description for detailed information. Reset and Interrupt The ATtiny15L provides eight interrupt sources. These interrupts and the separate Reset Vector each have a separate Program Vector in the Program memory space. All Handling the interrupts are assigned individual enable bits that must be set (one) together with the I-bit in the Status Register in order to enable the interrupt ...
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... MAIN: <instr> … … … The ATtiny15L has four sources of Reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V ). POR • External Reset. The MCU is reset when a low-level is present on the RESET pin for more than 500 ns. • ...
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... Figure 12. Reset Logic Table 4. Reset Characteristics (V Note: ATtiny15L 14 Power-on Reset Circuit Brown-out BODEN Reset Circuit BODLEVEL Reset Circuit Watchdog Timer Watchdog Oscillator Tunable Internal Oscillator CKSEL[1:0] CC Symbol Parameter Power-on Reset Threshold Voltage (rising) V POT Power-on Reset Threshold (1) Voltage (falling) RESET Pin Threshold ...
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... RESET after V period of the delay counter can be defined by the user through the CKSEL Fuses. The different selections for the delay period are presented in Table 5. The RESET signal is activated again, without any delay, when the V ATtiny15L Start-up Time 2.7V ...
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... An External Reset is generated by a low-level on the RESET pin. Reset pulses longer than 500 ns will generate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches the Reset Threshold Voltage (V period t Figure 15. External Reset during Operation ATtiny15L 16 V POT VCC V ...
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... Brown-out Detection Watchdog Reset 1187H–AVR–09/07 ATtiny15L has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during the operation. The BOD circuit can be enabled/disabled by the fuse BODEN. When BODEN is enabled (BODEN programmed), and V the trigger level, the Brown-out Reset is immediately activated. When V above the trigger level, the Brown-out Reset is deactivated after a delay ...
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... MCUSR Reset. • Bit 7..4 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. • Bit 3 – WDRF: Watchdog Reset Flag This bit is set (one Watchdog Reset occurs. The bit is reset (zero Power-on Reset writing a logical “0” to the flag. ...
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... Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny15L and always reads as zero. • Bit 6 – INT0: External Interrupt Request 0 Enable When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated ...
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... The General Interrupt Flag Register – GIFR • Bit 7 – Res: Reserved Bit This bit is a reserved bit in the ATtiny15L and always reads as zero. • Bit 6 – INTF0: External Interrupt Flag0 When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set (one) ...
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... Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $005) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set (one) in the Timer/Counter Interrupt Flag Register (TIFR). • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the ATtiny15L and always reads as zero. Bit 7 6 ...
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... Ove rflow Inte rrup t En able set (o ne Timer/Counter0 Overflow interrupt is executed. • Bit 0 – Res: Reserved Bit This bit is a reserved bit in the ATtiny15L and always reads as zero. External Interrupt The External Interrupt is triggered by the INT0 pin. Observe that, if enabled, the interrupt will trigger even if the INT0 pin is configured as an output ...
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... For details, refer to “Sleep Modes” below. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny15L and always reads as zero. • Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0 The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask is set (one) ...
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... Fuses that define the Reset Time-out period. Tuneable Internal RC The internal RC Oscillator provides a fixed 1.6 MHz clock (nominal at 5V and 25°C). This internal clock is always the system clock of the ATtiny15L. This Oscillator can be Oscillator calibrated by writing the calibration byte (see page 55) to the OSCCAL Register. ...
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... The Timer/Counter1 Prescaler 1187H–AVR–09/07 The ATtiny15L provides two general purpose 8-bit Timer/Counters. The Timer/Counters have sepa caling selection from separate 10-bit prescalers. The Timer/Counter0 uses internal clock (CK) as the clock time base. The Timer/Counter1 may use either the internal clock (CK) or the fast peripheral clock (PCK) as the clock time base ...
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... Register – SFIOR • Bit 7..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. • Bit 2 – FOC1A: Force Output Compare 1A Writing a logical “1” to this bit forces a change in the Compare Match Output pin PB1 (OC1A) according to the values already set in COM1A1 and COM1A0 ...
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... Bits 7..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. • Bits – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0 The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer0. ...
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... Figure 21. Timer/Counter1 Block Diagram The two Status Flags (Overflow and Compare Match) are found in the Timer/Counter Interrupt Flag Register (TIFR). Control signals are found in the Timer/Counter Control Register (TCCR1). The interrupt enable/disable settings are found in the Timer/Counter Interrupt Mask Register (TIMSK). ATtiny15L 28 Bit 7 6 ...
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... In PWM mode, these bits have a different function. Refer to Table 12 for a detailed description.When changing the COM1A1/COM1A0 bits, the Output Compare 1A Interrupt must be disabled by clearing its Interrupt Enable bit in the TIMSK Register. Otherwise an interrupt can occur when the bits are changed. ATtiny15L ...
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... CK oscillator clock. The Timer/Counter1 – TCNT1 This 8-bit register contains the value of Timer/Counter1. Timer/Counter1 is implemented as an up-counter with read and write access. Due to synchronization of the CPU and Timer/Counter1, data written into Timer/Counter1 is delayed by one CPU clock cycle. ATtiny15L 30 CS13 CS12 CS11 0 ...
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... Note that in PWM mode, writing to the Output Compare OCR1A, the data value is first transferred to a temporary location. The value is latched into OCR1A when the Timer/Counter reaches OCR1B. This prevents the occurrence of odd-length PWM pulses (glitches) in the event of an unsynchronized OCR1A write. See Figure 22 for an example. ATtiny15L ...
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... Timer Overflow Interrupt1 operates exactly as in normal Timer/Counter mode, i.e executed when TOV1 is set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to the Timer Output Compare A Flag and interrupt. ATtiny15L 32 Synchronized OC1A Latch Unsynchronized OC1A Latch ...
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... T × – PCK ( ) × OCR1B + ATtiny15L 33 ...
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... Register – WDTCR • Bits 7..5 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and will always read as zero. • Bit 4 – WDTOE: Watchdog Turn-off Enable This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will not be disabled ...
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... Watchdog Timer is enabled. The different prescaling values and their corresponding time-out periods are shown in Table 15. Table 15. Watchdog Timer Prescale Select WDP2 WDP1 ATtiny15L WDP0 Time-out Period 0 16K cycles 1 32K cycles 0 64K cycles 1 128K cycles 0 256K cycles 1 512K cycles 0 1,024K cycles 1 2,048K cycles 35 ...
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... The EEPROM Address Register – EEAR • Bit 7, 6 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and will always read as zero. • Bit 5..0 – EEAR5..0: EEPROM Address The EEPROM Address Register (EEAR) specifies the EEPROM address in the 64 bytes EEPROM space ...
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... Bit 7..4 – RES: Reserved Bits These bits are reserved bits in the ATtiny15L and will always read as zero. • Bit 3 – EERIE: EEPROM Ready Interrupt Enable When the I-bits in SREG and EERIE are set (one), the EEPROM Ready Interrupt is enabled ...
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... Keep the AVR RESET active (low) during periods of insufficient power supply 2. Keep the AVR core in Power-down sleep mode during periods of low V 3. Store constants in Flash memory if the ability to change memory contents from ATtiny15L 38 Number of Calibrated RC Parameter Oscillator Cycles ...
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... ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut- ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logical “1” to the flag. ATtiny15L ...
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... Comparator Interrupt is activated. When cleared (zero), the interrupt is disabled. • Bit 2 – Res: Reserved Bit This bit is a reserved bit in the ATtiny15L and will always read as zero. • Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select These bits determine the comparator events that trigger the Analog Comparator Inter- rupt ...
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... Interrupt on ADC Conversion Complete • Sleep Mode Noise Canceler The ATtiny15L features a 10-bit successive approximation ADC. The ADC is connected to a 4-channel Analog Multiplexer that allows one differential voltage input and four sin- gle-ended voltage inputs constructed from the pins of Port B. The differential input (PB3, PB4) is equipped with a programmable gain stage, providing amplification step (20x) on the differential input voltage before the A/D conversion ...
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... LSB. The ADC can operate in two modes – Single Conversion and Free Running. In Single Conversion mode, each conversion will have to be initiated by the user. In Free Running ATtiny15L 42 8-BIT DATA BUS ADC MULTIPLEXER ...
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... ADC clock frequency. The ADPSn bits in ADCSR are used to generate a proper ADC clock input frequency from any CK frequency above 100 kHz. The prescaler starts counting from the moment ATtiny15L Reset 7-BIT ADC PRESCALER ADC CLOCK SOURCE ...
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... ADSC ADIF ADCH ADCL MUX and REFS Update ATtiny15L 44 The ADC is switched on (ADEN in ADCSR is set). The voltage reference source is changed (the REFS1..0 bits in ADMUX change value). A differential channel is selected (MUX2 in ADMUX is “1”). Note that subsequent conversions on the same channel are not extended conversions. ...
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... Figure 29. ADC Timing Diagram, Free Running Conversion One Conversion 11 Cycle Number ADC Clock ADSC ADIF ADCH ADCL Conversion Complete Table 18. ADC Conversion Time Sample & Hold Condition (Cycles from Start of Conversion) Extended Conversion Normal Conversions ATtiny15L Sign and MSB of Result Conversion Complete Next Conversion ...
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... Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conversions. For a complete description of this bit, see “The ADC Data Register – ADCL and ADCH” on page 49. ATtiny15L 46 sion mode must be selected and the ADC conversion complete interrupt must be enabled ...
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... Bits 4..3 – Res: Reserved Bits These bits are reserved bits in the ATtiny15L and always read as zero. • Bits 2..0 – MUX2..MUX0: Analog Channel and Gain Selection Bits 2..0 The value of these bits selects which analog input is connected to the ADC. In case of differential input (PB3 - PB4), gain selection is also made with these bits ...
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... When this bit is set (one) and the I-bit in SREG is set (one), the ADC Conversion Com- plete Interrupt is activated. • Bits 2..0 – ADPS2..ADPS0: ADC Prescaler Select Bits These bits determine the division factor between the CK frequency and the input clock to the ADC. See Table 21. Table 21. ADC Prescaler Selections ATtiny15L 48 ADPS2 ADPS1 0 0 ...
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... However, the user should take the following fact into consideration: The interrupt triggers once the result is ready to be read. In Free Running mode, the next conversion will start immediately when the interrupt triggers. If ADMUX is changed after the interrupt triggers, the next conversion has already started, and the old setting is used. ATtiny15L – ...
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... If conversion accuracy is critical, the noise level can be reduced by applying the following techniques: 1. The analog part of the ATtiny15L and all analog components in the application 2. Keep analog signal paths as short as possible. Make sure analog tracks run over 3. Use the ADC noise canceler function to reduce induced noise from the CPU. ...
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... Connecting unused pins directly to Vcc or GND is not recommended, since this may cause excessive currents if the pin is accidentally configured as an output. In ATtiny15L four Port B pins – PB2, PB3, PB4, and PB5 – have alternative functions as inputs for the ADC. If some Port B pins are configured as outputs essential that these do not switch when a conversion is in progress ...
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... PUD-bit in the MCUCR Register. Table 22. DDBn Effects on Port B Pins Note: On ATtiny15L, PB5 is input or open-drain output. Because this pin is used for 12V pro- gramming, there is no ESD protection diode limiting the voltage on the pin to V does not rise above V reset or enter Programming mode unintentionally ...
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... In Serial Programming mode, this pin serves as the serial data input, MOSI. In Normal mode, this pin also serves as the positive input of the On-chip Analog Comparator. In ATtiny15L, this pin can be chosen to be the reference voltage for the ADC. Refer to the section “The Analog-to-Digital Converter, Analog Multiplexer, and Gain Stages” for details. ...
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... CKSEL1..0 Fuses: See Table 5 on page 15 for which combination of CKSEL1..0 to use. Default value is “00” CK the RSTDISBL Fuse is programmed, then the programming hardware should apply +12V to PB5 while the ATtiny15L is in Power-on Reset. If not, the part can fail to enter Programming mode caused by drive contention on PB0 and/or PB5. . ...
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... Programming 1187H–AVR–09/07 The ATtiny15L has a one-byte calibration value for the internal RC Oscillator. This byte resides in the high byte of address $000 in the signature address space. To make use of this byte, it should be read from this location and written into the normal Flash Program memory ...
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... Any memory location can be verified by using the Read instruction, which 5. Power-off sequence: When writing or reading serial data to the ATtiny15L, data is clocked on the eigth rising edge of the 16 external clock pulses needed to generate the internal clock. See Figure 31, Figure 32, and Table 26 for an explanation. ...
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... Table 25. High-voltage Serial Programming Instruction Set for ATtiny15L Instruction Instr.1 PB0 0_1000_0000_00 Chip Erase PB1 0_0100_1100_00 PB2 x_xxxx_xxxx_xx PB0 0_0001_0000_00 Write Flash High and Low PB1 0_0100_1100_00 Address PB2 x_xxxx_xxxx_xx PB0 i_i _00 Write Flash PB1 0_0010_1100_00 Low Byte PB2 x_xxxx_xxxx_xx ...
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... Table 25. High-voltage Serial Programming Instruction Set for ATtiny15L Instruction Instr.1 PB0 0_0000_0100_00 Read Lock PB1 0_0100_1100_00 Bits PB2 x_xxxx_xxxx_xx PB0 0_0000_1000_00 Read PB1 Signature 0_0100_1100_00 Bytes x_xxxx_xxxx_xx PB2 PB0 0_0000_1000_00 Read PB1 Calibration 0_0100_1100_00 Byte PB2 x_xxxx_xxxx_xx Note address high bits ...
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... Program memory and $000 to $03F for EEPROM memory. VALID IVSH SHIX SHSL SHOV Min 25.0 25.0 50.0 50.0 10.0 2.7 - 5.5V ATtiny15/L PB5 (RESET) VCC SCK PB2 MISO PB1 MOSI GND PB0 ATtiny15L t SLSH 16 = 25°C ± 10%, A Typ Max Units 16.0 32 ...
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... MHz). The minimum low and high periods for the serial clock (SCK) input are defined as follows: Low-voltage Serial When writing serial data to the ATtiny15L, data is clocked on the rising edge of SCK. Programming Algorithm When reading data from the ATtiny15L, data is clocked on the falling edge of SCK. See Figure 34, Figure 35, and Table 28 for timing details ...
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... WD_PROG_EE t and t values. WD_PROG_FL WD_PROG_EE Figure 34. Low-voltage Serial Programming Waveforms SERIAL DATA INPUT MSB PB0(MOSI) SERIAL DATA OUTPUT MSB PB1(MISO) SERIAL CLOCK INPUT PB2(SCK) before programming the next WD_PROG_FL before programming the next byte. See Table 30 for ATtiny15L LSB LSB 61 ...
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... – low byte, 1 – high byte o = data out i = data don’t care 1 = Lock bit Lock bit CKSEL0 Fuse 4 = CKSEL1 Fuse 5 = RSTDISBL Fuse 6 = SPIEN Fuse 7 = BODEN Fuse 8 = BODLEVEL Fuse ATtiny15L 62 (1) Instruction Format Byte 2 Byte 3 Byte4 0101 0011 xxxx xxxx xxxx xxxx 100x xxxx xxxx xxxx ...
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... SHOX t SCK Low to MISO Valid SLIV Table 29. Minimum Wait Delay after the Chip Erase Instruction Symbol t WD_ERASE Table 30. Minimum Wait Delay after Writing a Flash or EEPROM Location Symbol t WD_FLASH t WD_EEPROM ATtiny15L t t SLSH SHOX t SHSL A Min Typ = 2.7 - 5.5V) 0.8 1 2.7 - 5.5V) 625 ...
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... PB5 (4) Output High Voltage V OH Port B Input Leakage Current I IL I/O Pin Input Leakage Current I IH I/O Pin R I/O Pin Pull-up I/O I Power Supply Current CC ATtiny15L 64 *NOTICE: + 0.5V CC Condition Min Except (XTAL) -0.5 XTAL -0.5 (2) Except (XTAL, RESET) 0 (2) XTAL 0 RESET ...
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... Power-down is 1.5V (only with BOD disabled). CC 1187H–AVR–09/07 Condition Min -50 2. 4.0V CC may exceed the related specification. OL may exceed the related specification. Pins are not guaranteed to source current OH ATtiny15L Typ Max Units 40.0 50.0 750.0 500 3V) under steady state 5V, 1 3V) under steady state ...
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... I/O pin. The difference between current consumption in Power-down mode with Watchdog Timer enabled and Power-down mode with Watchdog Timer disabled represents the dif- ferential current drawn by the Watchdog Timer. Figure 36. Active Supply Current vs. V ATtiny15L 66 •V •f where C = load capacitance, V ...
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... Figure 38. Calibrated Internal RC Oscillator Frequency vs. V Relative Calibrated RC Oscillator Frequency vs. Operating Voltage 1.02 1.00 0.98 0.96 0.94 0.92 0.90 0.88 2 2.5 3 Note: The nominal calibrated RC oscillator frequency is 1.6 MHz. ATtiny15L ˚ 4.5 5 5 ˚ 25˚ ...
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... Figure 39. Bandgap Voltage vs. V Figure 40. Analog Comparator Offset Voltage vs. Common Mode Voltage Note: ATtiny15L 68 CC BANDGAP VOLTAGE vs. V MEASURED WITH ANALOG COMPARATOR 1.301 1.3 1.299 1.298 1.297 1.296 1.295 1.294 1.293 1.292 1.5 2 2.5 3 3.5 V ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE ...
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... Figure 41. Analog Comparator Offset Voltage vs. Common Mode Voltage ANALOG COMPARATOR OFFSET VOLTAGE vs. COMMON MODE VOLTAGE 0.5 1 Common Mode Voltage (V) Figure 42. Analog Comparator Input Leakage Current ANALOG COMPARATOR INPUT LEAKAGE CURRENT -10 0 0.5 1 1.5 2 2.5 ATtiny15L ˚ 1 ˚ 3.5 4 4.5 5 5.5 6 6 ˚ ...
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... Figure 43. Watchdog Oscillator Frequency vs. V Note: Figure 44. Pull-up Resistor Current vs. Input Voltage ATtiny15L 70 WATCHDOG OSCILLATOR FREQUENCY vs. V 1600 1400 1200 1000 800 600 400 200 0 1,5 2 2,5 3 3,5 1. Sink and source capabilities of I/O ports are measured on one pin at a time. PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ...
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... Figure 45. Pull-up Resistor Current vs. Input Voltage PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE ˚ ˚ 0.5 1 Figure 46. I/O Pin Sink Current vs. Output Voltage I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 1 ATtiny15L V = 2.7V cc 1.5 2 2 ˚ ˚ A 1.5 2 2 ...
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... Figure 47. I/O Pin Source Current vs. Output Voltage Figure 48. I/O Pin Sink Current vs. Output Voltage ATtiny15L 72 I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0 I/O PIN SINK CURRENT vs. OUTPUT VOLTAGE 0.5 V 2.5 3 3.5 4 4 ˚ ˚ 1.5 2 (V) OL 1187H–AVR–09/07 ...
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... Figure 49. I/O Pin Source Current vs. Output Voltage I/O PIN SOURCE CURRENT vs. OUTPUT VOLTAGE ˚ ˚ 0.5 1 Figure 50. I/O Pin Input Threshold Voltage vs. V I/O PIN INPUT THRESHOLD VOLTAGE vs. V 2.5 2 1.5 1 0.5 0 2.7 ATtiny15L V = 2.7V cc 1.5 2 2 ˚ 5.0 73 ...
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... Figure 51. I/O Pin Input Hysteresis vs. V ATtiny15L 74 CC I/O PIN INPUT HYSTERESIS vs 0.18 0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02 0 2.7 4 ˚ 5 1187H–AVR–09/07 ...
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... ATtiny15L Register Summary Address Name Bit 7 $3F SREG I $3E Reserved $3C Reserved $3B GIMSK - $3A GIFR - $39 TIMSK - $38 TIFR - $37 Reserved $36 Reserved $35 MCUCR - $34 MCUSR - $33 TCCR0 - $32 TCNT0 $31 OSCCAL $30 TCCR1 CTC1 $2F TCNT1 $2E OCR1A $2D OCR1B $2C SFIOR - $2B Reserved $2A Reserved $29 Reserved $28 Reserved $27 Reserved $26 Reserved $25 Reserved $24 Reserved $23 Reserved $22 Reserved $21 WDTCR - $20 Reserved $1F Reserved ...
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... ATtiny15L Instruction Set Summary Mnemonic Operands Description ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add Two Registers ADC Rd, Rr Add with Carry Two Registers SUB Rd, Rr Subtract Two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr Subtract with Carry Two Registers ...
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... ATtiny15L Instruction Set Summary (Continued) Mnemonic Operands Description CBI P, b Clear Bit in I/O Register LSL Rd Logical Shift Left LSR Rd Logical Shift Right ROL Rd Rotate Left through Carry ROR Rd Rotate Right through Carry ASR Rd Arithmetic Shift Right SWAP Rd Swap Nibbles BSET s Flag Set ...
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... Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green. ATtiny15L 78 Ordering Code Package ATtiny15L-1PC 8P3 (1) ATtiny15L-1PU 8P3 ATtiny15L-1SC 8S2 (1) ATtiny15L-1SU 8S2 ATtiny15L-1PI 8P3 (1) ATtiny15L-1PU 8P3 ATtiny15L-1SI 8S2 (1) ATtiny15L-1SU 8S2 Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) 1187H–AVR–09/07 ...
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... Wide, Plastic Dual Inline Package (PDIP) 8S2 8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 1187H–AVR–09/07 Package Type ATtiny15L 79 ...
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... D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch and eA measured with the leads constrained to be perpendicular to datum. 5. Pointed or rounded lead tips are preferred to ease insertion and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm). 2325 Orchard Parkway San Jose, CA 95131 R ATtiny15L ...
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... San Jose, CA 95131 R 1187H–AVR–09/ TOP VIEW TOP VIEW SIDE VIEW SIDE VIEW TITLE 8S2, 8-lead, 0.209" Body, Plastic Small Outline Package (EIAJ) ATtiny15L θ θ END VIEW END VIEW COMMON DIMENSIONS (Unit of Measure = mm) MIN NOM MAX SYMBOL A 1.70 2.16 A1 0.05 ...
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... Datasheet revision history Rev H - 09/07 1. Updated “Ordering Information” on page 78. Rev G - 06/07 1. “Not recommended for new design” Rev F - 06/05 1. Updated V 2. Added “Unconnected Pins” on page 51. 3. Updated “Packaging Information” on page 80. ATtiny15L Table 4 on page 14 BOT . 1187H–AVR–09/07 ...
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... Features................................................................................................. 1 Pin Configuration.................................................................................. 1 Description ............................................................................................ 2 Block Diagram ...................................................................................................... 3 Pin Descriptions.................................................................................................... 4 Internal Oscillators ............................................................................................... 4 ATtiny15L Architectural Overview ...................................................... 5 The General Purpose Register File ...................................................................... 6 The ALU – Arithmetic Logic Unit........................................................................... 6 The Flash Program Memory ................................................................................. 6 The Program and Data Addressing Modes .......................................................... 7 Subroutine and Interrupt Hardware Stack ............................................................ 9 The EEPROM Data Memory ................................................................................ 9 I/O Memory ...
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... High-voltage Serial Programming Characteristics .............................................. 59 Low-voltage Serial Downloading ........................................................................ 59 Low-voltage Serial Programming Characteristics............................................... 63 Electrical Characteristics................................................................... 64 Absolute Maximum Ratings ................................................................................ 64 DC Characteristics.............................................................................................. 64 Typical Characteristics ...................................................................... 66 ATtiny15L Register Summary............................................................ 75 ATtiny15L Instruction Set Summary................................................. 76 Ordering Information.......................................................................... 78 Packaging Information ....................................................................... 79 8P3 ..................................................................................................................... 79 8S2 ..................................................................................................................... 80 Datasheet revision history................................................................. 81 Rev H - 09/07...................................................................................................... 81 Rev G - 06/07 ..................................................................................................... 81 Rev F - 06/05 ...................................................................................................... 81 Table of Contents .................................................................................. i 1187H– ...
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... Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI- TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT ...