ATTINY15L-1SU Atmel, ATTINY15L-1SU Datasheet - Page 46

• Manufacturer Part Number: ATTINY15L-1SU
• Description: IC MCU AVR 1K FLASH 1.6MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY15L-1SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1.6MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Ram Size: -
• Connectivity: -

ADC Noise Canceler
Function
The ADC Multiplexer Selection
Register – ADMUX
46
ATtiny15L
The ADC features a noise canceler that enables conversion during ADC Noise Reduc-
tion mode (see “Sleep Modes” on page 23) to reduce noise induced from the CPU core
and other I/O peripherals. If other I/O peripherals must be active during conversion, this
mode works equivalently for Idle mode. To make use of this feature, the following proce-
dure should be used:
1. Make sure that the ADC is enabled and is not busy converting. Single Conver-
2. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conver-
3. If no other interrupts occur before the ADC conversion completes, the ADC inter-
• Bits 7..6 – REFS1..REFS0: Reference Selection Bits
These bits select the voltage reference for the ADC, as shown in Table 19. If these bits
are changed during a conversion, the change will not go into effect until this conversion
is complete (ADIF in ADCSR is set). Whenever these bits are changed, the next
conversion will take 25 ADC clock cycles. If active channels are used, using AVCC or an
external AREF higher than (AVCC - 1V) is not recommended, as this will affect ADC
accuracy. The internal voltage reference options may not be used if an external
reference voltage is being applied to the AREF pin.
Table 19. Voltage Reference Selections for ADC
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data
Register. If ADLAR is cleared, the result is right-adjusted. If ADLAR is set, the result is
left-adjusted. Changing the ADLAR bit will affect the ADC Data Register immediately,
regardless of any ongoing conversions. For a complete description of this bit, see “The
ADC Data Register – ADCL and ADCH” on page 49.
Bit
$07
Read/Write
Initial Value
REFS1
sion mode must be selected and the ADC conversion complete interrupt must be
enabled.
ADEN = 1
ADSC = 0
ADFR = 0
ADIE = 1
sion once the CPU has been halted.
rupt will wake up the MCU and execute the ADC conversion complete interrupt
routine.
0
0
1
1
REFS0
0
1
0
1
REFS1
R/W
7
0
Voltage Reference Selection
V
External Voltage Reference at PB0 (AREF) pin, Internal Voltage
Reference turned off.
Internal Voltage Reference without external bypass capacitor,
disconnected from PB0 (AREF).
Internal Voltage Reference with external bypass capacitor at PB0 (AREF)
pin.
CC
REFS0
R/W
used as analog reference, disconnected from PB0 (AREF).
6
0
ADLAR
R/W
5
0
R
4
–
0
R
3
–
0
MUX2
R/W
2
0
MUX1
R/W
1
0
MUX0
R/W
0
0
1187H–AVR–09/07
ADMUX