ATTINY15L-1SU Atmel, ATTINY15L-1SU Datasheet - Page 60

• Manufacturer Part Number: ATTINY15L-1SU
• Description: IC MCU AVR 1K FLASH 1.6MHZ 8SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY15L-1SU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 1.6MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 6
• Program Memory Size: 1KB (512 x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Ram Size: -
• Connectivity: -

Low-voltage Serial
Programming Algorithm
60
ATtiny15L
The device is clocked from the internal clock at the uncalibrated minimum frequency
(0.8 - 1.6 MHz). The minimum low and high periods for the serial clock (SCK) input are
defined as follows:
When writing serial data to the ATtiny15L, data is clocked on the rising edge of SCK.
When reading data from the ATtiny15L, data is clocked on the falling edge of SCK. See
Figure 34, Figure 35, and Table 28 for timing details. To program and verify the
ATtiny15L in the Serial Programming mode, the following sequence is recommended
(See 4-byte instruction formats in Table 27):
1. Power-up sequence:
2. Wait for at least 20 ms and enable serial programming by sending the Program-
3. The serial programming instructions will not work if the communication is out of
4. If a Chip Erase is performed (must be done to erase the Flash), wait t
5. The Flash or EEPROM array is programmed one byte at a time by supplying the
6. Any memory location can be verified by using the Read instruction, which
7. At the end of the programming session, RESET can be set high to commence
8. Power-off sequence (if needed):
Low: > 2 MCU clock cycles
High: > 2 MCU clock cycles
Apply power between V
grammer cannot guarantee that SCK is held low during Power-up, RESET must be
given a positive pulse of at least two MCU cycles duration after SCK has been set to
“0”.
ming Enable serial instruction to the MOSI (PB0) pin. Refer to the above section
for minimum low and high periods for the serial clock input SCK.
synchronization. When in sync, the second byte ($53) will echo back when issu-
ing the third byte of the Programming Enable instruction. Whether the echo is
correct or not, all four bytes of the instruction must be transmitted. If the $53 did
not echo back, give SCK a positive pulse and issue a new Programming Enable
instruction. If the $53 is not seen within 32 attempts, there is no functional device
connected.
after the instruction, give RESET a positive pulse, and start over from step 2.
See Table 29 on page 63 for t
address and data together with the appropriate write instruction. An EEPROM
memory location is first automatically erased before new data is written. Use
data polling to detect when the next byte in the Flash or EEPROM can be written.
If polling is not used, wait t
mitting the next instruction. See Table 30 on page 63 for the t
t
programmed.
returns the content at the selected address at the serial output MISO (PB1) pin.
normal operation.
Set RESET to “1”.
Turn V
WD_PROG_EE
CC
power off.
values. In an erased device, no $FFs in the data file(s) need to be
CC
and GND while RESET and SCK are set to “0”. If the pro-
WD_PROG_FL
WD_ERASE
or t
value.
WD_PROG_EE
, respectively, before trans-
WD_PROG_FL
WD_ERASE
1187H–AVR–09/07
and