AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 17

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

8.1.1
Table 8-3.
Note:
8.1.1.1
8.1.1.2
8.1.1.3
8.1.1.4
8.1.2
6242E–ATARM–11-Sep09
Address
0x0000 0000
1. EBI NCS0 is to be connected to a 16-bit non-volatile memory. The access configuration is defined by the reset state of SMC
Internal Memory Mapping
Boot Strategies
Setup, SMC Pulse, SMC Cycle and SMC Mode CS0 registers.
Internal SRAM
Internal ROM
LCD Controller
USB Host Port
Internal Memory Mapping
Master 0: ARM926 Instruction
REMAP(RCB0) = 0
BMS = 1
Int. ROM
Table 8-3
status and the BMS state at reset.
The AT91SAM9261S embeds a high-speed 16-Kbyte SRAM.
The AT91SAM9261S integrates a 32-Kbyte Internal ROM mapped at address 0x0040 0000. It is
also accessible at address 0x0 after reset and before remap if the BMS is tied high during reset.
The AT91SAM9261S integrates a USB Host Port Open Host Controller Interface (OHCI). The
registers of this interface are directly accessible on the AHB Bus and are mapped like a standard
internal memory at address 0x0050 0000.
The AT91SAM9261S integrates an LCD Controller. The interface is directly accessible on the
AHB Bus and is mapped like a standard internal memory at address 0x0060 0000.
The system always boots at address 0x0. To ensure a maximum number of possibilities for boot,
the memory layout can be configured with two parameters.
REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This
is done by software once the system has booted for each Master of the Bus Matrix. Refer to the
Bus Matrix Section for more details.
When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an
external memory. This is done via hardware at reset.
Note:
The AT91SAM9261S Bus Matrix manages a boot memory that depends on the level on the
BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is
reserved for this purpose.
If BMS is detected at 1, the boot memory is the embedded ROM.
If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the
External Bus Interface.
Memory blocks not affected by these parameters can always be seen at their specified base
addresses. See the complete memory map presented in
BMS = 0
EBI NCS0
summarizes the Internal Memory Mapping for each Master, depending on the Remap
(1)
Int. RAM C
REMAP (RCB0) = 1
Master 1: ARM926 Data
REMAP (RCB1) = 0
BMS = 1
Int. ROM
Figure 8-1 on page
BMS = 0
EBI NCS0
AT91SAM9261S
(1)
REMAP (RCB1) = 1
Int. RAM C
15.
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