AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 674
![no-image](/images/manufacturer_photos/0/0/78/atmel_sml.jpg)
AT91SAM9261SB-CU-999
Manufacturer Part Number
AT91SAM9261SB-CU-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261SB-CU-999.pdf
(709 pages)
Specifications of AT91SAM9261SB-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, I2S, SPI, USB
Maximum Clock Frequency
190 MHz
Number Of Programmable I/os
96
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
Minimum Operating Temperature
- 40 C
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
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42.2.9.8
42.2.10
42.2.10.1
42.2.10.2
42.2.10.3
674
AT91SAM9261S
Serial Synchronous Controller (SSC)
SPI: Software Reset Must be Written Twice
SSC: Transmitter Limitations in Slave Mode
SSC: Periodic Transmission Limitations in Master Mode
SSC: Last RK Clock Cycle when RK Outputs a Clock During Data Transfer
Do not use a multiple Chip Select configuration where at least one SCRx register is configured
with SCBR = 1 and the others differ from 1 if NCPHA = 0 and CPOL = 1.
If all chip selects are configured with Baudrate = 1, the issue does not appear.
If a software reset (SWRST in the SPI control register) is performed, the SPI may not work prop-
erly (the clock is enabled before the chip select).
The SPI Control Register field SWRST (Software Reset) needs to be written twice to be correctly
set.
If TK is programmed as input and TF is programmed as output and requested to be set to
low/high during data emission, the Frame Synchro is generated one bit clock period after the
data start, one data bit is lost. This problem does not exist when generating periodic synchro.
The data need to be delayed for one bit clock period with an external assembly.
In the following schematic, TD, TK and NRST are AT91SAM9261S signals, TXD is the delayed
data to connect to the device.
If the Least Significant Bit is sent first (MSBF = 0) the first TAG during the frame synchro is not
sent.
None.
When the SSC receiver is used with the following conditions:
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
6242E–ATARM–11-Sep09
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