AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 689

• Manufacturer Part Number: AT91SAM9261SB-CU-999
• Description: IC MCU ARM9 ULTRA LP 217LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9261SB-CU-999

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 190MHz
• Connectivity: EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: 2-Wire, I2S, SPI, USB
• Maximum Clock Frequency: 190 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
• Minimum Operating Temperature: - 40 C
• For Use With: AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

42.3.15.2
42.3.15.3
42.3.15.4
42.3.16
42.3.16.1
42.3.16.2
6242E–ATARM–11-Sep09
UHP
USART: TXD Signal is Floating in Modem and Hardware Handshaking Mode
USART: DCD is Active High Instead of Low
USART: CTS signal in Hardware Handshake
UHP: Non-ISO IN Transfers
UHP: ISO OUT Transfers
TXD signal should be pulled up in Modem and Hardware Handshaking mode.
TXD is multiplexed with a PIO which integrates a pull-up resistor. This internal pullup needs to
be enabled.
DCD signal is active at “High” level in USART block (Modem Mode).
DCD should be active at “Low” level.
Add an inverter.
When Hardware Handshaking is used and if CTS goes low near the end of the starting bit of the
transmitter, a character is lost.
CTS must not go low during a time slot comprised between 2 Master Clock periods before the
rising edge of the starting bit, and 16 Master Clock periods after the rising edge of the starting
bit.
Conditions:
Consider the following sequence:
Consequence: When this defect manifests itself, the Host controller re-attempts the same IN
token.
This problem can be avoided if the system guarantees that the status update can be completed
within the same frame.
Conditions:
Consider the following sequence:
1. The Host controller issues an IN token.
2. The Device provides the IN data in a short packet.
3. The Host controller writes the received data to the system memory.
4. The Host controller is now supposed to carry out two Write transactions (TD status
5. The Host controller raises the request for the first write transaction. By the time the
6. After completing the first write transaction, the Host controller skips the second write
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
write and TD retirement write) to the system memory in order to complete the status
update.
transaction is completed, a frame boundary is crossed.
transaction.
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