AT91SAM9261SB-CU-999 Atmel, AT91SAM9261SB-CU-999 Datasheet - Page 678
AT91SAM9261SB-CU-999
Manufacturer Part Number
AT91SAM9261SB-CU-999
Description
IC MCU ARM9 ULTRA LP 217LFBGA
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM9261SB-CU-999.pdf
(709 pages)
Specifications of AT91SAM9261SB-CU-999
Core Processor
ARM9
Core Size
16/32-Bit
Speed
190MHz
Connectivity
EBI/EMI, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
DMA, LCD, POR, PWM, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
1.08 V ~ 1.32 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
217-LFBGA
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
16 KB
Interface Type
2-Wire, I2S, SPI, USB
Maximum Clock Frequency
190 MHz
Number Of Programmable I/os
96
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9261-EK
Minimum Operating Temperature
- 40 C
For Use With
AT91SAM9261-EK - KIT EVAL FOR AT91SAM926EJ-SAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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42.2.16.2
42.2.16.3
678
AT91SAM9261S
UHP: ISO OUT Transfers
UHP: Remote Wakeup Event
Consequence: When this defect manifests itself, the Host controller re-attempts the same IN
token.
This problem can be avoided if the system guarantees that the status update can be completed
within the same frame.
Conditions:
Consider the following sequence:
Consequence: After the failure condition, the Host controller stops sending the SOF. This
causes the connected device to go into suspend state.
This problem can be avoided if the system can guarantee that no buffer underrun occurs during
the transfer.
Conditions:
When a Remote Wakeup event occurs on a downstream port, the OHCI Host controller begins
sending resume signaling to the device. The Host controller is supposed to send this resume
signaling for 20 ms. However, if the driver sets the HcControl.HCFS into USBOPERATIONAL
state during the resume event, then the Host controller terminates sending the resume signal
with an EOP to the device.
Consequence: If the Device does not recognize the resume (<20 ms) event, then the Device will
remain in suspend state.
Host stack can do a port resume after it sets the HcControl.HCFS to USBOPERATIONAL.
4. The Host controller is now supposed to carry out two Write transactions (TD status
5. The Host controller raises the request for the first write transaction. By the time the
6. After completing the first write transaction, the Host controller skips the second write
1. The Host controller sends an ISO OUT token after fetching 16 bytes of data from the
2. When the Host controller is sending the ISO OUT data, because of system latencies,
3. While there is an underrun condition, if the Host controller is in the process of bit-stuff-
Problem Fix/Workaround
Problem Fix/Workaround
Problem Fix/Workaround
write and TD retirement write) to the system memory in order to complete the status
update.
transaction is completed, a frame boundary is crossed.
transaction.
system memory.
remaining bytes of the packet are not available. This results in a buffer underrun
condition.
ing, it causes the Host controller to hang.
6242E–ATARM–11-Sep09
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