HD6473837H Renesas Electronics America, HD6473837H Datasheet - Page 116

• Manufacturer Part Number: HD6473837H
• Description: IC H8 MCU OTP 60K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473837H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 84
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.2
5.2.1
The system goes from active mode to sleep mode when a SLEEP instruction is executed while the
SSBY and LSON bits in system control register 1 (SYSCR1) are cleared to 0. In sleep mode CPU
operation is halted but the on-chip peripheral functions other than PWM are operational. The CPU
register contents are retained.
5.2.2
Sleep mode is cleared by an interrupt (timer A, timer B, timer C, timer F, timer G, IRQ
WKP
Clearing by Interrupt: When an interrupt is requested, sleep mode is cleared and interrupt
exception handling starts. Operation resumes in active (high-speed) mode if MSON = 0 in
SYSCR2, or active (medium-speed) mode if MSON = 1. Sleep mode is not cleared if the I bit of
the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the interrupt
enable register.
Clearing by RES Input: When the RES pin goes low, the CPU goes into the reset state and sleep
mode is cleared.
5.3
5.3.1
The system goes from active mode to standby mode when a SLEEP instruction is executed while
the SSBY bit in SYSCR1 is set to 1, the LSON bit is cleared to 0, and bit TMA3 in timer
register A (TMA) is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and
on-chip peripheral modules stop functioning. As long as a minimum required voltage is applied,
the contents of CPU registers and some on-chip peripheral registers, and data in the on-chip RAM,
are retained. Data in the on-chip RAM will be retained as long as the specified RAM data
retention voltage is supplied. The I/O ports go to the high-impedance state.
0
to WKP
Sleep Mode
Transition to Sleep Mode
Clearing Sleep Mode
Standby Mode
Transition to Standby Mode
7
, SCI1, SCI2, SCI3, A/D converter) or by input at the RES pin.
0
to IRQ
4
,
99