HD6473837H Renesas Electronics America, HD6473837H Datasheet - Page 273

• Manufacturer Part Number: HD6473837H
• Description: IC H8 MCU OTP 60K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473837H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 84
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bit 5—Transmit Enable (TE): Bit 5 enables or disables the start of a transmit operation.
Bit 5: TE
0
1
Notes: 1. The transmit data register empty bit (TDRE) in the serial status register (SSR) is fixed
Bit 4—Receive Enable (RE): Bit 4 enables or disables the start of a receive operation.
Bit 4: RE
0
1
Notes: 1. When RE is cleared to 0, this has no effect on the SSR flags RDRF, FER, PER, and
Bit 3—Multiprocessor Interrupt Enable (MPIE): Bit 3 enables or disables multiprocessor
interrupt requests. This setting is valid only in asynchronous mode, and only when the
multiprocessor mode bit (MP) in the serial mode register (SMR) is set to 1. This bit is ignored
when COM is set to 1 or when bit MP is cleared to 0.
Bit 3: MPIE
0
1
Note: * SCI3 does not transfer receive data from RSR to RDR, does not detect receive errors, and
256
does not set status flags RDRF, FER, and OER in SSR. Until a multiprocessor bit value of 1
is received, the receive data full interrupt (RXI) and receive error interrupt (ERI) are
disabled and serial status register (SSR) flags RDRF, FER, and OER are not set. When the
multiprocessor bit receives a 1, the MPBR bit of SSR is set to 1, MPIE is automatically
cleared to 0, RXI and ERI interrupts are enabled (provided bits TIE and RIE in SCR3 are
set to 1), and setting of the RDRF, FER, and OER flags is enabled.
2. In this state, writing transmit data in TDR clears bit TDRE in SSR to 0 and starts serial
2. Serial data receiving begins when, in this state, a start bit is detected in asynchronous
Before setting TE to 1 it is necessary to set the transmit format in SMR.
Before setting RE to 1 it is necessary to set the receive format in SMR.
at 1.
data transmission.
OER, which retain their states.
mode, or serial clock input is detected in synchronous mode.
Description
Transmit operation disabled
Transmit operation enabled
Description
Receive operation disabled
Receive operation enabled
Description
Multiprocessor interrupt request disabled (ordinary receive operation)
Clearing condition:
Multiprocessor bit receives a data value of 1
Multiprocessor interrupt request enabled*
*
*
*
*
2
1
2
1
(RXD is the receive data pin)
(RXD is a general I/O port)
(TXD is the transmit data pin)
(TXD is a general I/O port)
(initial value)
(initial value)
(initial value)