HD6473837H Renesas Electronics America, HD6473837H Datasheet - Page 294

• Manufacturer Part Number: HD6473837H
• Description: IC H8 MCU OTP 60K 100QFP
• Manufacturer: Renesas Electronics America
• Series: H8® H8/300Lr

Specifications of HD6473837H

• Core Processor: H8/300L
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: SCI
• Peripherals: LCD, PWM
• Number Of I /o: 84
• Program Memory Size: 60KB (60K x 8)
• Program Memory Type: OTP
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 75°C
• Package / Case: 100-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

SCI3 operates as follows when receiving serial data in asynchronous mode.
SCI3 monitors the communication line, and when a start bit (0) is detected it performs internal
synchronization and starts receiving. The communication format for data receiving is as outlined
in table 10.16. Received data is set in RSR from LSB to MSB, then the parity bit and stop bit(s)
are received. After receiving the data, SCI3 performs the following checks:
If no receive error is detected by the above checks, bit RDRF is set to 1 and the received data is
stored in RDR. At that time, if bit RIE in SCR3 is set to 1, an RXI interrupt is requested. If the
error check detects a receive error, the appropriate error flag (OER, PER, or FER) is set to 1.
RDRF retains the same value as before the data was received. If at this time bit RIE in SCR3 is set
to 1, an ERI interrupt is requested.
Table 10.17 gives the receive error detection conditions and the processing of received data in
each case.
Note: Data receiving cannot be continued while a receive error flag is set. Before continuing the
Table 10.17 Receive Error Conditions and Received Data Processing
Receive Error
Overrun error
Framing error
Parity error
Parity check: The number of 1s received is checked to see if it matches the odd or even parity
selected in bit PM of SMR.
Stop bit check: The stop bit is checked for a value of 1. If there are two stop bits, only the first
bit is checked.
Status check: The RDRF bit is checked for a value of 0 to make sure received data can be
transferred from RSR to RDR.
receive operation it is necessary to clear the OER, FER, PER, and RDRF flags to 0.
Abbrev.
OER
FER
PER
Detection Conditions
Receiving of the next data ends while
bit RDRF in SSR is still set to 1
Stop bit is 0
Received data does not match the
parity (odd/even) set in SMR
Received Data Processing
Received data is not
transferred from RSR to RDR
Received data is transferred
from RSR to RDR
Received data is not
transferred from RSR to RDR
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