MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 127

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

10.1.2 Analog Converter
10.1.3 Digital Control
10.1.4 Result Registers
TECHNICAL DATA
Conversion of an analog input selected by the multiplexer occurs in this block. It con-
tains a digital-to-analog capacitor (DAC) array, a comparator, and a successive ap-
proximation register (SAR). Each conversion is a sequence of eight comparison
operations, beginning with the most significant bit (MSB). Each comparison deter-
mines the value of a bit in the successive approximation register.
The DAC array performs two functions. It acts as a sample and hold circuit during the
entire conversion sequence, and provides comparison voltage to the comparator dur-
ing each successive comparison.
The result of each successive comparison is stored in the SAR. When a conversion
sequence is complete, the contents of the SAR are transferred to the appropriate re-
sult register.
A charge pump provides switching voltage to the gates of analog switches in the mul-
tiplexer. Charge pump output must stabilize between 7 and 8 volts, thus a delay of up
to 100 s must be imposed after setting ADPU before the converter can be used. The
charge pump is enabled by the ADPU bit in the OPTION register.
Power is provided to the A/D converter system through the AV
All A/D converter operations are controlled by bits in register ADCTL. In addition to se-
lecting the analog input to be converted, ADCTL bits indicate conversion status, and
control whether single or continuous conversions are performed. Finally, the ADCTL
bits determine whether conversions are performed on single or multiple channels.
Four 8-bit registers (ADR1–ADR4) store conversion results. Each of these registers
can be accessed by the processor in the CPU. The conversion complete flag (CCF)
ANALOG
Figure 10-2 Electrical Model of an A/D Input Pin (Sample Mode)
INPUT
PIN
Freescale Semiconductor, Inc.
< 2 pF
*
PROTECTION
This analog switch is closed only during the 12-cycle sample time.
For More Information On This Product,
DEVICE
INPUT
ANALOG-TO-DIGITAL CONVERTER
+
–
~
~
20 V
0.7 V
Go to: www.freescale.com
JUNCTION
LEAKAGE
DIFFUSION AND
POLY COUPLER
400 nA
4 k
*
DD
V
RL
and AV
~
CAPACITANCE
20 pF
DAC
SS
pins.
10-3