MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 92

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

R8 — Receive Data Bit 8
T8 — Transmit Data Bit 8
M — Mode (Select Character Format)
WAKE — Wakeup by Address Mark/Idle
7.6.3 Serial Communications Control Register 2
SCCR2 — SCI Control Register 2
TIE — Transmit Interrupt Enable
TCIE — Transmit Complete Interrupt Enable
RIE — Receiver Interrupt Enable
ILIE — Idle-Line Interrupt Enable
TE — Transmitter Enable
RE — Receiver Enable
7-6
RESET:
If M bit is set, R8 stores the ninth bit in the receive data character.
If M bit is set, T8 stores the ninth bit in the transmit data character.
The SCCR2 register provides the control bits that enable or disable individual SCI
functions.
When TE goes from zero to one, one unit of idle character time (logic one) is queued
as a preamble.
0 = Start bit, 8 data bits, 1 stop bit
1 = Start bit, 9 data bits, 1 stop bit
0 = Wakeup by IDLE line recognition
1 = Wakeup by address mark (most significant data bit set)
0 = TDRE interrupts disabled
1 = SCI interrupt requested when TDRE status flag is set
0 = TC interrupts disabled
1 = SCI interrupt requested when TC status flag is set
0 = RDRF and OR interrupts disabled
1 = SCI interrupt requested when RDRF flag or the OR status flag is set
0 = IDLE interrupts disabled
1 = SCI interrupt requested when IDLE status flag is set
0 = Transmitter disabled
1 = Transmitter enabled
0 = Receiver disabled
1 = Receiver enabled
Bit 7
TIE
0
TCIE
6
0
Freescale Semiconductor, Inc.
For More Information On This Product,
SERIAL COMMUNICATIONS INTERFACE
RIE
5
0
Go to: www.freescale.com
ILIE
4
0
TE
0
3
RE
2
0
RWU
1
0
TECHNICAL DATA
Bit 0
SBK
0
MC68HC11F1
$102D