MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 49

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

RAM[3:0] — RAM Map Position
REG[3:0] — 128-Byte Register Block Position
4.3.2.3 OPTION Register
OPTION — System Configuration Options
TECHNICAL DATA
RESET:
These four bits, which specify the upper hexadecimal digit of the RAM address, control
position of RAM in the memory map. RAM can be positioned at the beginning of any
4-Kbyte page in the memory map. Refer to Table 4-5.
These four bits specify the upper hexadecimal digit of the address for the 128-byte
block of internal registers. The register block is positioned at the beginning of any 4-
Kbyte page in the memory map. Refer to Table 4-5.
When the memory map has the 96-byte register block mapped at the same location
as RAM, the registers have priority and the lower 96 bytes of RAM are inaccessible.
No harmful conflicts occur due to a hardware resource priority scheme. On-chip reg-
isters have the highest priority of all on-chip resources, followed by on-chip RAM, boot-
strap ROM, and on-chip EEPROM.
The 8-bit special-purpose OPTION register sets internal system configuration options
during initialization. In single-chip and expanded modes (SMOD = 0), IRQE, DLY, FC-
ME, and CR[1:0] can be written only once and only in the first 64 cycles after a reset.
This minimizes the possibility of any accidental changes to the system configuration.
In special test and bootstrap modes (SMOD = 1), these bits can be written at any time.
*Can be written only once in first 64 cycles out of reset in normal modes or at any time in special modes.
RAM[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
ADPU
Bit 7
0
CSEL
$C000–$C3FF
$D000–$D3FF
$A000–$A3FF
$B000–$B3FF
$E000–$E3FF
$0000–$03FF
$1000–$13FF
$2000–$23FF
$3000–$33FF
$4000–$43FF
$5000–$53FF
$6000–$63FF
$7000–$73FF
$8000–$83FF
$9000–$93FF
$F000–$F3FF
6
0
Freescale Semiconductor, Inc.
Location
OPERATING MODES AND ON-CHIP MEMORY
Table 4-5 RAM and Register Mapping
For More Information On This Product,
IRQE*
5
0
Go to: www.freescale.com
DLY*
4
0
CME
0
3
REG[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
FCME*
2
0
CR1*
1
0
$A000–$A05F
$B000–$B05F
$C000–$C05F
$D000–$D05F
$E000–$E05F
$F000–$F05F
$0000–$005F
$1000–$105F
$2000–$205F
$3000–$305F
$4000–$405F
$5000–$505F
$6000–$605F
$7000–$705F
$8000–$805F
$9000–$905F
Location
CR0*
Bit 0
0
$1039
4-11