MCHC11F1CFNE3 Freescale Semiconductor, MCHC11F1CFNE3 Datasheet - Page 46

• Manufacturer Part Number: MCHC11F1CFNE3
• Description: IC MCU 8BIT 1K RAM 68-PLCC
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MCHC11F1CFNE3

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 68-PLCC
• A/d Inputs: 8-Channel, 8-Bit
• Eeprom Memory: 512 Bytes
• Input Output: 30
• Interface: SCI/SPI
• Memory Type: EPROM
• Number Of Bits: 8
• Package Type: 68-pin PLCC
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 3-5.5 V
• Controller Family/series: 68HC11
• No. Of I/o's: 30
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 3MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Processor Series: HC11F
• Core: HC11
• Data Bus Width: 8 bit
• Program Memory Size: 512 B
• Data Ram Size: 1 KB
• Interface Type: SCI, SPI
• Maximum Clock Frequency: 3 MHz
• Number Of Timers: 1
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 8 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Size: -
• Lead Free Status / Rohs Status: RoHS Compliant part

4.3.1.1 HPRIO Register
HPRIO — Highest Priority I-Bit Interrupt and Miscellaneous
RBOOT — Read Bootstrap ROM
SMOD and MDA — Special Mode Select and Mode Select A
IRV — Internal Read Visibility
PSEL[3:0] — Priority Select Bits [3:0]
4-8
RESET:
A normal mode is selected when MODB is logic one during reset. One of three reset
vectors is fetched from address $FFFA–$FFFF, and program execution begins from
the address indicated by this vector. If MODB is logic zero during reset, the special
mode reset vector is fetched from addresses $BFFA–$BFFF and software has access
to special test features. Refer to SECTION 5 RESETS AND INTERRUPTS for infor-
mation regarding reset vectors.
Bits in the HPRIO register select the highest priority interrupt level, select whether
bootstrap ROM is present, and control visibility of internal reads by the CPU. After re-
set, MDA and SMOD select the operating mode.
*Reset states of RBOOT, SMOD, and MDA bits depend on hardware mode selection. Refer to Table 4-3.
Set to one out of reset in bootstrap mode. Valid while in special modes only. Can be
read anytime. Can only be written in special modes.
The initial value of SMOD is the inverse of the logic level present on the MODB pin at
the rising edge of reset. The initial value of MDA equals the logic level present on the
MODA pin at the rising edge of reset. These two bits can be read at any time. They can
be written at any time in special modes. Neither bit can be written is normal modes.
SMOD cannot be set once it has been cleared. Refer to Table 4-3.
IRV can be written at any time in special modes (SMOD = 1). In normal modes (SMOD
= 0) IRV can be written only once. In expanded and test modes, IRV determines
whether internal read visibility is on or off. In single-chip and bootstrap modes, IRV has
no meaning or effect.
Refer to 5.3.1 Highest Priority Interrupt and Miscellaneous Register.
0 = Bootloader ROM disabled and not in map
1 = Bootloader ROM enabled and in map at $BF00–$BFFF
0 = No internal read visibility on external bus
1 = Data from internal reads is driven out the external data bus.
RBOOT*
Bit 7
0
0
1
0
SMOD*
0
0
1
1
6
Freescale Semiconductor, Inc.
OPERATING MODES AND ON-CHIP MEMORY
For More Information On This Product,
MDA*
5
0
1
0
1
Go to: www.freescale.com
IRV
4
0
0
1
1
PSEL3
3
0
0
0
0
PSEL2
2
1
1
1
1
PSEL1
1
1
1
1
1
PSEL0
Bit 0
TECHNICAL DATA
0
0
0
0
MC68HC11F1
Single Chip
Expanded
Bootstrap
Special Test
$103C