ATA5428-PLQW Atmel, ATA5428-PLQW Datasheet - Page 55

• Manufacturer Part Number: ATA5428-PLQW
• Description: IC TXRX WIDEBND 433/868MHZ 48QFN
• Manufacturer: Atmel

Specifications of ATA5428-PLQW

• Frequency: 433MHz, 868MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Alarm and Security Systems, RKE
• Power - Output: 10dBm
• Sensitivity: -112.5dBm
• Voltage - Supply: 2.4 V ~ 3.6 V or 4.4 V ~ 6.6 V
• Current - Receiving: 10.5mA
• Current - Transmitting: 10mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Height (mm): 0.9mm
• Product Length (mm): 7mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: ATA5428-PLQHCT; ATA5428-PLQHCT; ATA5428-PLQWCT

Figure 9-2.
4841D–WIRE–10/07
Sleep mode:
All circuits for analog signal processing are disabled. Only XTO and Polling logic is enabled.
Output level on pin RX_ACTIVE
T
Start-up mode:
Bit-check mode:
The incomming data stream is analyzed. If the timing indicates a valid transmitter signal,
the control bits VSOUT_EN, CLK_ON and OPM0 are set to 1 and the transceiver is set to
receiving mode. Otherwise the transceiver is set to Sleep mode
(if OPM0 = 0 and T
Output level on pin RX_ACTIVE
I
Receiving mode:
The incomming data stream is passed via PIN SDO_TMDO to the connected
microcontroller. If an bit error occurs the transceiver is not set back to Start-up mode.
Output level on pin RX_ACTIVE
I
S
S
Sleep
= I
= I
Start-up PLL:
The PLL is enabled and locked.
Output level on pin RX_ACTIVE
Start-up signal processing:
The signal processing circuit are enabled.
Output level on pin RX_ACTIVE
RX_X
RX_X
= Sleep
Start RX Mode
NO
; T
Flow Chart Polling Mode/RX Mode (T_MODE = 1, Transparent Mode Active)
Bit-check
1024
T
Sleep
OPM0 = 1
SLEEP
?
?
T
> 0) or stays in Bit-check mode.
DCLK
YES
YES
= 0
Start RX Polling Mode
X
Sleep
Low; I
High
High
RX data stream
available on pin
NO
High; I
High; I
SDO_TMDO
Level on pin
CS = Low ?
S
= I
NO
S
S
IDLE_X
= I
= I
YES
Startup_PLL_X
RX_X
Set VSOUT_EN = 1
Set CLK_ON = 1
; T
Set OPM0 = 1
Bit check
Startup_Sig_proc
OK ?
NO
; I
ATA5423/ATA5425/ATA5428/ATA5429
YES
Startup_PLL
Sleep:
X
T
T
T
T
DCLK
Startup_PLL
Startup_Sig_Proc
Bit-check
Sleep
:
:
:
:
:
Defined by bits Sleep 0 to Sleep 4 in Control
Register 4
Defined by bit XSleep in Control register 4
Basic clock cycle
798.5
882
498
306
210
Is defined by the selected baud rate range and
T
Baud 0 and Baud 1 in Control Register 6.
Depends on the result of the bit check.
If the bit check is ok, T
number of bits to be checked (N
on the utilized data rate.
If the bit check fails, the average time period for
that check despends on the selected bit-rate
range and on T
defined by bit Baud 0 and Baud 1 in Control
Register 6.
If in FSK mode the datastream is interrupted the
FSK-Demodulator-PLL tends to lock out and is
further not able to lock in, even there is a valid
data stream available.
In this case the transceiver must be set back to
IDLE mode.
DCLK
T
T
T
T
.The baud-rate range is defined by bit
DCLK
DCLK
DCLK
DCLK
T
DCLK
(typ)
XDCLK
(BR_Range 0)
(BR_Range 1)
(BR_Range 2)
(BR_Range 3)
. The bit-rate range is
Bit-check
depends on the
Bit-check
) and
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