ATA5428-PLQW Atmel, ATA5428-PLQW Datasheet - Page 58

• Manufacturer Part Number: ATA5428-PLQW
• Description: IC TXRX WIDEBND 433/868MHZ 48QFN
• Manufacturer: Atmel

Specifications of ATA5428-PLQW

• Frequency: 433MHz, 868MHz
• Data Rate - Maximum: 20kbps
• Modulation Or Protocol: ASK, FSK
• Applications: Alarm and Security Systems, RKE
• Power - Output: 10dBm
• Sensitivity: -112.5dBm
• Voltage - Supply: 2.4 V ~ 3.6 V or 4.4 V ~ 6.6 V
• Current - Receiving: 10.5mA
• Current - Transmitting: 10mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 7mm
• Product Height (mm): 0.9mm
• Product Length (mm): 7mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Memory Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: ATA5428-PLQHCT; ATA5428-PLQHCT; ATA5428-PLQWCT

Figure 9-6.
Figure 9-7.
9.1.6
58
Bit-check counter
Bit-check counter
ATA5423/ATA5425/ATA5428/ATA5429
Duration of the Bit Check
(Lim_min = 14, Lim_max = 24)
(Lim_min = 14, Lim_max = 24)
RX_ACTIVE
RX_ACTIVE
Demod_Out
Demod_Out
Timing Diagram for Failed Bit Check (Condition CV_Lim < Lim_min)
Timing Diagram for Failed Bit Check (Condition: CV_Lim
Bit check
Bit check
T
Start-up mode
T
Start-up mode
Startup_Sig_Proc
Startup_Sig_Proc
If no transmitter is present during the bit check, the output of the ASK/FSK demodulator delivers
random signals. The bit check is a statistical process and T
fore, an average value for T
the selected bit-rate range and on T
T
Bit-check
0
0
, resulting in a lower current consumption in RX polling mode.
Bit check failed (CV_Lim < Lim_min)
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112
1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 9 101112
Bit check mode
T
Bit_check
1/2 Bit
1/2 Bit
Bit check mode
Bit check failed (CV_Lim < Lim_min)
Bit-check
T
Bit_check
is given in the electrical characteristics. T
XDCLK
131415161718192021222324
. A higher bit-rate range causes a lower value for
Lim_max)
Sleep mode
Bit-check
T
Sleep
0
varies for each check. There-
Sleep mode
T
Sleep
0
Bit-check
4841D–WIRE–10/07
depends on