XR20M1172IL32-F Exar Corporation, XR20M1172IL32-F Datasheet - Page 10
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XR20M1172IL32-F
Manufacturer Part Number
XR20M1172IL32-F
Description
IC UART FIFO I2C/SPI 64B 32QFN
Manufacturer
Exar Corporation
Datasheet
1.XR20M1172IG28-F.pdf
(58 pages)
Specifications of XR20M1172IL32-F
Number Of Channels
2, DUART
Package / Case
32-VFQFN Exposed Pad
Features
*
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
1.62 V ~ 3.63 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
16 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.62 V
Supply Current
250 uA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
No. Of Channels
2
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
1.62V To 3.63V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFN
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR20M1172IL32-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
The SPI interface consists of four lines: serial clock (SCL), chip select (CS#), slave output (SO) and slave input
(SI). The serial clock, slave output and slave input can be as fast as 5 Mbps. To access the device in the SPI
mode, the CS# signal for the M1172 is asserted by the SPI master, then the SPI master starts toggling the SCL
signal with the appropriate transaction information. The first bit sent by the SPI master includes whether it is a
read or write transaction and the UART register being accessed. See
F
F
2.1.2
IGURE
IGURE
7. SPI W
8. SPI R
SPI Bus Interface
EAD
RITE
SCLK
SCLK
SI
SI
B
6:3
2:1
7
0
IT
R/W A3
R/W A3
SO
Read/Write#
Logic 1 = Read
Logic 0 = Write
UART Internal Register Address A3:A0
UART Channel Select
’00’ = UART Channel A
’01’ = UART Channel B
Other values are reserved
Reserved
A2
A2
A1
A1
T
ABLE
A0 CH1 CH0 X
A0 CH1 CH0 X
3: SPI F
D7
D7
IRST
10
D6
D6
F
UNCTION
D5
D5
B
YTE
D4
D4
D3
D3
F
ORMAT
D2
D2
D1
D1
Table 3
D0
D0
below.
REV. 1.0.1