XR20M1172IL32-F Exar Corporation, XR20M1172IL32-F Datasheet - Page 25
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XR20M1172IL32-F
Manufacturer Part Number
XR20M1172IL32-F
Description
IC UART FIFO I2C/SPI 64B 32QFN
Manufacturer
Exar Corporation
Datasheet
1.XR20M1172IG28-F.pdf
(58 pages)
Specifications of XR20M1172IL32-F
Number Of Channels
2, DUART
Package / Case
32-VFQFN Exposed Pad
Features
*
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
1.62 V ~ 3.63 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
16 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.62 V
Supply Current
250 uA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
No. Of Channels
2
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
1.62V To 3.63V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFN
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR20M1172IL32-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
REV. 1.0.1
The complete register set is shown below in
3.0 UART INTERNAL REGISTERS
A
DDRESS
0X00
0X00
0X01
0X02
0X01
0X02
0X03
0X04
0X05
0X06
0X07
0X06
0X07
0X08
0x0C
0x0D
0x09
0x0A
0x0B
0x0E
0x0F
0x02
0x04
0x05
0x06
0x07
RHR - Receive Holding Register
THR - Transmit Holding Register
DLL - Divisor LSB
DLM - Divisor MSB
DLD - Divisor Fractional
IER - Interrupt Enable Register
ISR - Interrupt Status Register
FCR - FIFO Control Register
LCR - Line Control Register
MCR - Modem Control Register
LSR - Line Status Register
MSR - Modem Status Register
SPR - Scratch Pad Register
TCR - Transmission Control Register
TLR - Trigger Level Register
TXLVL - Transmit FIFO Level
RXLVL - Receive FIFO Level
IODir - GPIO Direction Control Register
IOState - GPIO State Register
IOIntEna - GPIO Interrupt Enable Register
Reserved
IOControl - GPIO Control Register
EFCR - Extra Features Control Register
EFR - Enhanced Function Register
Xon-1 - Xon Character 1
Xon-2 - Xon Character 2
Xoff-1 - Xoff Character 1
Xoff-2 - Xoff Character 2
T
ABLE
7: UART INTERNAL REGISTER ADDRESSES
16C550 C
R
EGISTER
Table 7
OMPATIBLE
and
25
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
Table
R
EGISTERS
8.
R
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Read-only
Read-only
Read-only
Read-only
Write-only
Write-only
EAD
/W
-
RITE
LCR[7] = 1, LCR ≠ 0xBF,
LCR[7] = 1, LCR ≠ 0xBF
See
See
See
See
LCR = 0xBF
LCR ≠ 0xBF
C
LCR[7] = 0
EFR[4] = 1
LCR[7] = 0
LCR[7] = 0
XR20M1172
OMMENTS
Table 12
Table 13
Table 12
Table 13