XR20M1172IL32-F Exar Corporation, XR20M1172IL32-F Datasheet - Page 9

• Manufacturer Part Number: XR20M1172IL32-F
• Description: IC UART FIFO I2C/SPI 64B 32QFN
• Manufacturer: Exar Corporation

Specifications of XR20M1172IL32-F

• Number Of Channels: 2, DUART
• Package / Case: 32-VFQFN Exposed Pad
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 1.62 V ~ 3.63 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 16 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.62 V
• Supply Current: 250 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 1.62V To 3.63V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.1
There could be many devices on the I
are eight possible slave addresses that can be selected for the M1172 using the A1 and A0 address lines.
Table 1
select each I2C address.
An I
UART register address being accessed. A read or write transaction is determined by bit-0 of the slave address
(
After the last read or write transaction, the I
HIGH = Read, LOW = Write).
2.1.1.1
2
C sub-address is sent by the I
below shows the different addresses that can be selected. Note that there are two different ways to
I
2
C-bus Addressing
B
6:3
2:1
7
0
IT
GND
GND
GND
GND
VCC
VCC
VCC
VCC
SDA
SDA
SDA
SDA
SCL
SCL
SCL
SCL
Table 2
A1
T
ABLE
Reserved
UART Internal Register Address A3:A0
UART Channel Select
’00’ = UART Channel A
’01’ = UART Channel B
other values are reserved
Reserved
T
ABLE
below lists the functions of the bits in the I
2
2: I C S
2
VCC
GND
VCC
GND
VCC
GND
VCC
GND
SDA
SDA
SDA
SDA
C master following the slave address. The sub-address contains the
SCL
SCL
SCL
SCL
C-bus. To distinguish itself from the other devices on the I
A0
2
1: XR20M1172 I C A
2
C-bus master will set the SCL signal back to its idle state (HIGH).
UB
-A
DDRESS
9
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
F
UNCTION
0x60 (0110 000X)
0x62 (0110 001X)
0x64 (0110 010X)
0x68 (0110 100X)
0x6A (0110 101X)
0x6C (0110 110X)
0x60 (0110 000X)
0x62 (0110 001X)
0x64 (0110 010X)
0x68 (0110 100X)
0x6A (0110 101X)
0x6C (0110 110X)
0x66 (0110 011X)
0x6E (0110 111X)
0x66 (0110 011X)
0x6E (0110 111X)
2
(R
I
2
C A
EGISTER
DDRESS
DDRESS
A
M
DDRESS
AP
2
)
C sub-address.
XR20M1172
2
C-bus, there