XR20M1172IL32-F Exar Corporation, XR20M1172IL32-F Datasheet - Page 7

• Manufacturer Part Number: XR20M1172IL32-F
• Description: IC UART FIFO I2C/SPI 64B 32QFN
• Manufacturer: Exar Corporation

Specifications of XR20M1172IL32-F

• Number Of Channels: 2, DUART
• Package / Case: 32-VFQFN Exposed Pad
• Features: *
• Fifo's: 64 Byte
• Protocol: RS485
• Voltage - Supply: 1.62 V ~ 3.63 V
• With Auto Flow Control: Yes
• With Irda Encoder/decoder: Yes
• With False Start Bit Detection: Yes
• With Modem Control: Yes
• With Cmos: Yes
• Mounting Type: Surface Mount
• Data Rate: 16 Mbps
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.62 V
• Supply Current: 250 uA
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• No. Of Channels: 2
• Uart Features: Tx/Rx FIFO Counters
• Supply Voltage Range: 1.62V To 3.63V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: QFN
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REV. 1.0.1
The M1172 can operate with either an I
the I2C/SPI# input pin.
The I
bus interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial
clock and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to
400 kbps. The first byte sent by an I
when SCL is HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-
address that contains the address of the register to access. The M1172 responds to each write with an
acknowledge (SDA driven LOW by M1172 for one clock cycle when SCL is HIGH). If the TX FIFO is full, the
M1172 will respond with a negative acknowledge (SDA driven HIGH by M1172 for one clock cycle when SCL is
HIGH) when the CPU tries to write to the TX FIFO. The last byte sent by an I
transition from LOW to HIGH when SCL is HIGH). See
I
F
F
F
2
2.0 FUNCTIONAL DESCRIPTIONS
2.1
2.1.1
IGURE
IGURE
IGURE
C-bus specifications.
SDA
SCL
White block: host to UART
Grey block: UART to host
S
2
C-bus interface is compliant with the Standard-mode and Fast-mode I
3. I C S
4. M
5. M
CPU Interface
ADDRESS
SLAVE
I
2
C-bus Interface
2
ASTER
ASTER
START condition
TART AND
S
W
R
White block: host to UART
Grey block: UART to host
W
EADS
S
RITES
A
S
F
T
ADDRESS
ROM
TOP
O
SLAVE
REGISTER
ADDRESS
S
LAVE
C
S
ONDITIONS
LAVE
(M1172)
2
2
C-bus master contains a start bit (SDA transition from HIGH to LOW
C-bus interface or an SPI interface. The CPU interface is selected via
(M1172)
W
A
A
S
REGISTER
ADDRESS
ADDRESS
SLAVE
7
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
Figures 3
R
A
A
-
5
nDATA
below. For complete details, see the
nDATA
2
2
C-bus master is a stop bit (SDA
C-bus specifications. The I
A
A
STOP condition
P
LAST DATA
P
XR20M1172
NA
P
2
C-