XR20M1172IL32-F Exar Corporation, XR20M1172IL32-F Datasheet - Page 40
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XR20M1172IL32-F
Manufacturer Part Number
XR20M1172IL32-F
Description
IC UART FIFO I2C/SPI 64B 32QFN
Manufacturer
Exar Corporation
Datasheet
1.XR20M1172IG28-F.pdf
(58 pages)
Specifications of XR20M1172IL32-F
Number Of Channels
2, DUART
Package / Case
32-VFQFN Exposed Pad
Features
*
Fifo's
64 Byte
Protocol
RS485
Voltage - Supply
1.62 V ~ 3.63 V
With Auto Flow Control
Yes
With Irda Encoder/decoder
Yes
With False Start Bit Detection
Yes
With Modem Control
Yes
With Cmos
Yes
Mounting Type
Surface Mount
Data Rate
16 Mbps
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.62 V
Supply Current
250 uA
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
No. Of Channels
2
Uart Features
Tx/Rx FIFO Counters
Supply Voltage Range
1.62V To 3.63V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
QFN
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XR20M1172IL32-F
Manufacturer:
EXAR/艾科嘉
Quantity:
20 000
XR20M1172
TWO CHANNEL I2C/SPI UART WITH 64-BYTE FIFO
DLD[5:4]: Sampling Rate Select
These bits select the data sampling rate. By default, the data sampling rate is 16X. The maximum data rate will
double if the 8X mode is selected and will quadruple if the 4X mode is selected. See
DLD[7:6]: Reserved
Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive
character software flow control selection (see
are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that
whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before
programming a new setting.
EFR[3:0]: Software Flow Control Select
Single character and dual sequential characters software flow control is supported. Combinations of software
flow control can be selected by programming these bits.
4.21
EFR
C
ONT
X
X
X
0
0
1
0
1
1
0
1
0
Enhanced Feature Register (EFR)
BIT
-3
-3
DLD[5]
0
0
1
EFR
C
ONT
X
X
X
0
0
0
1
1
0
1
1
0
BIT
-2
-2
T
ABLE
EFR
C
ONT
15: S
T
X
X
X
X
0
0
1
0
1
1
1
1
ABLE
BIT
-1
-1
OFTWARE
14: S
Table
EFR
C
AMPLING
ONT
DLD[4]
15). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes
X
X
X
X
0
0
0
1
1
1
1
1
F
BIT
LOW
40
-0
X
0
1
-0
C
R
No TX and RX flow control (default and reset)
No transmit flow control
Transmit Xon1, Xoff1
Transmit Xon2, Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1, Xoff1
Receiver compares Xon2, Xoff2
Transmit Xon1, Xoff1
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Transmit Xon2, Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
No transmit flow control,
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
ONTROL
ATE
T
RANSMIT AND
S
ELECT
F
UNCTIONS
R
ECEIVE
S
Table 14
S
OFTWARE
AMPLING
16X
8X
4X
F
R
below.
LOW
ATE
C
REV. 1.0.1
ONTROL