HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 118

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 36
5.10
5.10.1
Cortina Systems
Byte Swapper Behavior
TAP Interface (JTAG)
The IXF1104 MAC includes an IEEE 1149.1 compliant Test Access Port (TAP) interface
used during boundary scan testing. The interface consists of the following five signals:
TDI and TMS require external pull-up resistors to float the signals High per the IEEE 1149.1
specification. Pull-ups are recommended on TCLK and TDO. For normal operation,
TRST_L can be pulled Low, permanently disabling the JTAG interface. If the JTAG interface
is used, the TAP controller must be reset as described in
Machine, on page 118
TAP State Machine
The TAP signals drive a TAP controller, which implements the 16-state state machine
specified by the IEEE 1149.1 specification. Following power-up, the TAP controller must be
reset by one of following two mechanisms:
Asynchronous reset is achieved by pulsing or holding TRST_L Low. Synchronous reset is
achieved by clocking TCLK with five clock pulses while TMS is held or floats High. This
ensures that the boundary scan cells do not block the pin to core connections in the
IXF1104 MAC.
®
1. In 8-bit mode, data is output in Little Endian format regardless of the IXF1104 MAC Endian setting.
UPX_BADD
• TDI – Serial Data Input
• TMS – Test Mode Select
• TCLK – TAP Clock
• TRST_L – Active Low asynchronous reset for the TAP
• TDO – Serial Data Output
• Asynchronous reset
• Synchronous reset
IXF1104 4-Port Gigabit Ethernet Media Access Controller
[1:0]
00
01
10
11
UPX_DATA_
[31:0]
32-bit
[31:0]
–
–
–
and returned to a logic High.
Little Endian
UPX_DATA
[15:0]
[31:16]
16-bit
[15:0]
–
–
UPX_DATA
[23:16]
[31:24]
8-bit
[7:0]
[15:8]
[7:0]
1
UPX_DATA
[31:0]
[31:24]
32-bit
[23:16
[15:8]
[7:0]
–
–
–
Section 5.10.1, TAP State
Big Endian
UPX_DATA
[15:0]
[23:16]
[31:24]
16-bit
[15:8]
[7:0]
–
–
UPX_DATA
[23:16]
[31:24]
8-bit
[7:0]
[15:8]
[7:0]
Page 118
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