HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 40

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 3
Cortina Systems
SPI3 Interface Signal Descriptions (Sheet 3 of 8)
®
MPHY
TMOD1
TMOD0
TSX
TADR1
TADR0
DTPA_0
DTPA_1
DTPA_2
DTPA_3
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Signal Name
SPHY
NA
NA
TADR1
TADR0
DTPA_0
DTPA_1
DTPA_2
DTPA_3
Designator
Ball
A12
A11
D9
A6
E1
D3
A9
L1
J7
Output
Type
Input
Input
Input
Standard
LVTTL
LVTTL
LVTTL
LVTTL
3.3 V
3.3 V
3.3 V
3.3 V
Description
TMOD[1:0] Transmit Word Modulo.
32-bit Multi-PHY mode: TMOD[1:0]
indicates the valid data bytes of TDAT[31:0].
During transmission, TMOD[1:0] should
always be “00” until the last double word is
transferred on TDAT[31:0]. TMOD[1:0]
specifies the valid bytes of TDAT when
TEOP is asserted:
TMOD[1:0] – Valid Bytes of TDAT
00 = 4 bytes [31:0]
01 = 3 bytes [31:8]
10 = 2 bytes [31:16]
11 = 1 byte [31:24]
TENB must be asserted simultaneously for
TMOD[1:0] to be valid.
4 x 8 Single-PHY mode: MOD[1:0] is not
required.
Transmit Start of Transfer.
32-bit Multi-PHY mode: TSX asserted with
TENB = 1 indicates that the PHY address is
present on TDAT[7:0]. The valid values on
TDAT[7:0] are 3, 2, 1, and 0. When
TENB = 0, TSX is not used by the PHY
device.
Note:
4 x 8 Single-PHY mode: TSX is not used.
TADR[1:0] Transmit PHY Address.
The value on TADR[1:0] selects one of the
PHY ports that drives the PTPA signal after
the rising edge of TFCLK.
DTPA_0:3 Direct Transmit Packet
Available.
A direct status indication for transmit FIFOs
of ports 0:3.
When High, DTPA indicates that the amount
of data in the TX FIFO is below the TX FIFO
High watermark. When the High watermark
is crossed, DTPA transitions Low to indicate
that the TX FIFO is almost full. It stays Low
until the amount of data in the TX FIFO
goes back below the TX FIFO Low
watermark. At this point, DTPA transitions
High to indicate that the programmed
number of bytes are now available for data
transfers.
Note:
DTPA is updated on the rising edge of
TFCLK.
Only TDAT[1:0] are relevant; all
other bits are “Don’t Care”.
For more information, see
131, TX FIFO High Watermark
Ports 0 - 3 ($0x600 – 0x603), on
page 193
Low Watermark Register Ports 0 - 3
($0x60A – 0x60D), on page
and
Table 132, TX FIFO
Table
195.
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