HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 70

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
5.1.2.1.3
Note:
5.1.2.1.4
5.1.2.1.5
Note:
Note:
Cortina Systems
The transmitted Pause Length in the IXF1104 MAC is set by the
The IXF1104 MAC PAUSE frame transmission interval is set by the
Response to Received PAUSE Command Frames
When Flow Control is enabled in the receive direction (bit 0 in the
+
partner as follows:
The IXF1104 MAC response to valid received PAUSE frames is independent of the PAUSE
frame filter settings. Refer to
additional details.
Pause packets are not filtered if flow control is disabled in bit 0 of the
Port_Index +
Half-Duplex Operation
Transmit flow control is implemented only in half-duplex operation. Upon entering the flow
control state, the MAC generates a collision for all subsequent receive packets until exiting
the flow control state. Any receive packet in progress when the MAC enters the flow control
state will not be collided with but could be lost due if there is insufficient FIFO depth to
complete packet reception. Bit 2 of the
transmit flow control function.
Transmit Pause Control Interface
The Transmit Pause Control interface allows an external device to trigger the generation of
pause frames. The Transmit Pause Control interface is completely asynchronous. It
consists of three address signals (TXPAUSEADD[2:0]) and a strobe signal (TXPAUSEFR).
The required address for this interface operation is placed on the TXPAUSEADD[2:0]
signals and the TXPAUSEFR is pulsed High and returned Low. Refer to
Pause Control Interface, on page 71
Parameters, on page
signals.
Flow control must be enabled in the
Control interface operation.
There are two additional decodes provided that allow the user to generate either an XOFF
frame or XON frame from all ports simultaneously.
The default pause quanta for each port is held by the
0x07)). The default value of this register is 0x05E after reset is applied.
®
1. The IXF1104 MAC checks the entire frame to verify that it is a valid PAUSE control
2. If the PAUSE frame is valid, the transmit side of the IXF1104 MAC pauses for the
3. PAUSE does not begin until completion of the frame currently being transmitted.
• Pause Threshold is the amount of time, measured in multiples of 512 bit times, prior to
0x12)), the IXF1104 MAC responds to PAUSE Command frames received from the link
IXF1104 4-Port Gigabit Ethernet Media Access Controller
the expiration of the Pause Length that the MAC transmits another Pause frame to
maintain the link partner in the pause state.
frame addressed to the Multicast Address 01-80-C2-00-00-01 (as specified in IEEE
802.3, Annex 31B) or has a Destinations Address matching the address programmed in
the
required number of PAUSE Quanta, as specified in IEEE 802.3, Clause 31.
Station Address ($ Port_Index +0x00 –
Figure 10
0x12).
illustrates the transmit pause control interface.
144.
Table 22
Section 5.1.1.3.5, Filter Pause Packets, on page 66
shows the valid decodes for the TXPAUSEADD[2:0]
FC Enable ($ Port_Index + 0x12)
and
FC Enable ($ Port_Index + 0x12)
Table 54, Transmit Pause Control Interface Timing
+0x01).
FC TX Timer Value ($ Port_Index +
Table 74 on page
FC Enable ($ Port_Index
Table 79 on page
FC Enable ($
for Transmit Pause
Figure 10, Transmit
enables the
for
157.
Page 70
158.