HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 120

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
5.11.1
Note:
Figure 33
Note:
5.11.2
Cortina Systems
SPI3 Interface Loopback
To provide a diagnostic loopback feature on the SPI3 interface, it is possible to configure the
IXF1104 MAC to loop back any data written to the IXF1104 MAC through the SPI3 transmit
interface back to the SPI3 receive interface. This is accomplished using the data path
shown in
Loopback packets also appear on the line side TX interface.
SPI3 Interface Loopback Path
There is a restriction when using this loopback mode. At least one clock cycle is required
between a TEOP assertion and a TSOP assertion. This is required when the pre-pend
feature of the receive FIFO is enabled to allow the addition of the extra two bytes to the data
sent on the transmit interface. Where the pre-pend feature has not been enabled, data can
be sent back-to-back on the transmit SPI3 interface with TSOP following TEOP on the next
cycle.
To configure the IXF1104 MAC to use the SPI3 loopback mode, the
Loopback Enable for Ports 0 - 3 ($0x5B2)
a unique bit in this register designated to control loopback. It is possible to have individual
ports in a loopback mode while other ports continue to operate in a normal mode.
Line Side Interface Loopback
To provide a diagnostic loopback feature on the line-side interfaces, the IXF1104 MAC can
be configured to loop back any data received by the IXF1104 MAC through one of the line
interfaces back to the corresponding transmit line interface. This is done by using the data
path shown in
Please note that it is not possible to loop one line-side interface back to a different one (for
example, Rx SerDes looped back to transmit RGMII).
®
IXF1104 4-Port Gigabit Ethernet Media Access Controller
TX
RX
Figure
SPI3 Interface
Block
Figure
33.
34. The line-side interface can be either SerDes, RGMII or GMII.
RX FIFO
SPI3 Internal Loopback
TX FIFO
must be configured. Each IXF1104 MAC port has
MAC
RX FIFO SPI3
Line Side
Interface
B3229-01
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