HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 173

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 93
8.4.4
Note:
Table 94
Cortina Systems
MAC TX Statistics ($ Port_Index +0x40 – +0x58) (Sheet 4 of 4)
PHY Autoscan Registers
These register hold the current values of the PHY registers only when Autoscan (see
Section 5.5.8, Autoscan Operation, on page
configured in copper mode. These registers are not applicable in fiber mode.
PHY Control ($ Port Index + 0x60) (Sheet 1 of 2)
®
Name
TxCRCError
TxPauseFrames
TxFlowControlCollisions
Send
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
1. RO = Read Only; RR = Clear on Read; W = Write; R/W = Read/Write
2. This register is ignored if auto-negotiation is enabled.
31:16
Bit
IXF1104 4-Port Gigabit Ethernet Media Access Controller
15
14
13
12
11
clear; R/W/C = Read/Write, Clear on Write
Name
Reserved
Reset
Loopback
Speed Selection
Auto-Negotiation
Enable
Power-Down
Description
Number of frames transmitted with a
legal size but with the wrong CRC field
(also called FCS field).
Number of pause MAC frames
transmitted.
Intentionally generates collisions to
curb reception of incoming traffic due to
insufficient memory available for
additional frames. The port must be in
half-duplex mode with flow control
enabled.
Note:
Note:
Reserved
Description
PHY Soft Reset. Resets the PHY registers to their
default value.
This register bit self-clears after the reset is
complete.
0 = Normal Operation
1 = PHY reset
0 = Disable loopback mode
1 = Enable loopback mode
0.6 (Speed<1> 0.13 (Speed<0>)
00 = 10 Mbps
01 = 100 Mbps
10 = 1000 Mbps (manual mode not allowed)
11 = Reserved
0 = Disable auto-negotiation process
1 = Enable auto-negotiation process
This register bit must be enabled for
1000BASE-T operation.
0 = Normal operation
1 = Power-down
To receive a correct statistic, a
last frame may have to be
transmitted after the last flow
control collisions send.
NA - half-duplex only
99) is enabled and the IXF1104 MAC is
Port_Index +
Port_Index +
Port_Index +
Address
0x56
0x57
0x58
Type
Type
RO
RO
RO
RO
RO
RO
R
R
R
1
1
0x00000010
0x00000000
0x00000000
0x00000000
Default
001000
0x0000
Default
0
0
0
1
0
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