HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 92

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
5.4
Note:
Figure 18
5.4.1
5.4.2
Cortina Systems
Reduced Gigabit Media Independent Interface (RGMII)
The IXF1104 MAC supports the RGMII interface standard as defined in the RGMII Version
1.2 specification. The RGMII interface is an alternative to the IEEE 802.3u MII interface.
The RGMII interface is intended as an alternative to the IEEE 802.3u MII and the IEEE
802.3z GMII. The principle objective of the RGMII is to reduce the number of balls (from a
maximum of 28 balls to 12 balls) required to interconnect the MAC and the PHY. This
reduction is both cost-effective and technology-independent. To accomplish this objective,
the data paths and all associated control signals are reduced, control signals are
multiplexed together, and both edges of the clock are used.
The IXF1104 MAC RGMII interface is multiplexed with signals from the GMII interface. See
Table 15, Line Side Interface Multiplexed Balls, on page 56
RGMII Interface
Multiplexing of Data and Control
Multiplexing of data and control information is achieved by utilizing both edges of the
reference clocks and sending the lower four bits on the rising edge and the upper four bits
on the falling edge. Control signals are multiplexed into a single clock cycle using the same
technique. For further information on timing parameters, see
Timing, on page 135
Timing Specifics
The IXF1104 MAC RGMII complies with RGMII Rev1.2a requirements.
the timing specifics.
®
• 1000 Mbps operation – clocks operate at 125 MHz
• 100 Mbps operation – clocks operate at 25 MHz
• 10 Mbps operation – clocks operate at 2.5 MHz.
IXF1104 4-Port Gigabit Ethernet Media Access Controller
and
Table 47, RGMII Interface Timing Parameters, on page
RX_EN_3:0
RX_ER_3:0
TX_EN_3:0
TX_ER_3:0
RXD[7:0]_0
RXD[7:0]_1
RXD[7:0]_2
RXD[7:0]_3
TXD[7:0]_0
TXD[7:0]_1
TXD[7:0]_2
TXD[7:0]_3
RXC_3:0
CRS_3:0
TXC_3:0
COL_3:0
TXC_3:0
TXD[7:0]_0
TXD[7:0]_1
TXD[7:0]_2
TXD[7:0]_3
TX_EN_3:0
TX_ER_3:0
RXC_3:0
RXD[7:0]_0
RXD[7:0]_1
RXD[7:0]_2
RXD[7:0]_3
RX_EN_3:0
RX_ER_3:0
CRS_3:0
COL_3:0
for detailed information.
Figure 37, RGMII Interface
B3203-02
Table 26
provides
135.
Page 92