HPIXF1104BE.B1-994579 Cortina Systems Inc, HPIXF1104BE.B1-994579 Datasheet - Page 193

• Manufacturer Part Number: HPIXF1104BE.B1-994579
• Description: IC ETH MAC SPI3 4PORT 552-BGA
• Manufacturer: Cortina Systems Inc

Specifications of HPIXF1104BE.B1-994579

• Controller Type: Ethernet Controller, MAC
• Interface: SPI-3
• Voltage - Supply: 1.2V, 2.5V, 3.3V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 575-BCBGA Exposed Pad (552 Bumps)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Current - Supply: -
• Other names: 1008-1020

IXF1104 MAC
Datasheet
278757, Revision 13.2
17 September 2008
Table 130
8.4.7
Table 131
Cortina Systems
RX FIFO Transfer Threshold Port 3 ($0x5BB)
TX FIFO Register Overview
Table 131
the TX FIFO High and Low watermark.
TX FIFO High Watermark Ports 0 - 3 ($0x600 – 0x603) (Sheet 1 of 2)
®
Register Description: RX FIFO transfer threshold for port 3 in 8-byte location.
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
Name
TX FIFO High
Watermark Port 0
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
31:12
IXF1104 4-Port Gigabit Ethernet Media Access Controller
11:0
Bit
clear; R/W/C = Read/Write, Clear on Write
clear; R/W/C = Read/Write, Clear on Write
Name
Reserved
RX FIFO Transfer
Threshold - Port 3
through
Description
High watermark for TX FIFO Port 0. The
default value of 0x3E0 represents 992 8-byte
locations. This equates to 7936 bytes of data. A
unit entry in this register equates to 8 bytes of
data. When the amount of data stored in the TX
FIFO exceeds the high watermark, flow control
is automatically initiated on the SPI3 interface to
request that the switch fabric stops data
transfers to avoid an overflow condition.
Table 138
Description
Reserved
RX FIFO transfer threshold for port 3. This must
be less than the RX FIFO High water mark.
User definable control register that sets the
threshold where a packet starts transitioning to the
SPI3 interface from the RX FIFO before the EOP
is received. Packets received in the RX FIFO
below this threshold are treated as store and
forward.
Note:
provide an overview of the TX FIFO registers, which include
Do not program the RX FIFO transfer
threshold below a setting of 0xBE
(1520bytes).
Address
0x600
Type
R/W
Type
R/W
RO
1
0x000000BE
0x000003E0
0x00000
Default
Default
0x0BE
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