LFXP2-30E-5FN484C Lattice, LFXP2-30E-5FN484C Datasheet - Page 141
LFXP2-30E-5FN484C
Manufacturer Part Number
LFXP2-30E-5FN484C
Description
FPGA - Field Programmable Gate Array 30KLUTs 363 I/O Inst -on DSP 1.2V -5 Spd
Manufacturer
Lattice
Specifications of LFXP2-30E-5FN484C
Number Of Macrocells
29000
Number Of Programmable I/os
363
Data Ram Size
396288
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-30E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
CLKDIV Inputs-to-Outputs Delay Matching
Figure 9-17. CLKDIV Inputs-to-Outputs Delay Matching
DCS (Dynamic Clock Select)
DCS is a global clock buffer incorporating a smart multiplexer function that takes two independent input clock
sources and avoids glitches or runt pulses on the output clock, regardless of where the enable signal is toggled.
There are two DCSs for each quadrant.
The outputs of the DCS then reach primary clock distribution via the feedlines. Figure 9-18 shows the block dia-
gram of the DCS.
Figure 9-18. DCS Primitive Symbol
DCS Primitive Definition
Table 9-10 defines the I/O ports of the DCS block. There are eight modes to select from. Table 9-11 describes how
each mode is configured.
Table 9-10. DCS I/O Definition
CLKI
CDIV1
CDIV2
CDIV4
CDIV8
Input
Output
I/O
DCSOUT
Name
CLK0
CLK1
SEL
CLK0
CLK1
SEL
9-19
DCS
DCSOUT
Input Clock Select
Clock Input 1
Clock input 0
Clock Output
Description
LatticeXP2 sysCLOCK PLL
Design and Usage Guide
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