LFXP2-30E-5FN484C Lattice, LFXP2-30E-5FN484C Datasheet - Page 180
![FPGA - Field Programmable Gate Array 30KLUTs 363 I/O Inst -on DSP 1.2V -5 Spd](/photos/16/15/161505/landingpagelatticexp2_sml.jpg)
LFXP2-30E-5FN484C
Manufacturer Part Number
LFXP2-30E-5FN484C
Description
FPGA - Field Programmable Gate Array 30KLUTs 363 I/O Inst -on DSP 1.2V -5 Spd
Manufacturer
Lattice
Specifications of LFXP2-30E-5FN484C
Number Of Macrocells
29000
Number Of Programmable I/os
363
Data Ram Size
396288
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-30E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Figure 10-31. FIFO_DC without Output Registers, End of Data Write Cycle
In this case, the Almost Full flag is in the 2 location before the FIFO_DC is filled. The Almost Full flag is asserted
when the N-2 location is written, and the Full flag is asserted when the last word is written into the FIFO_DC.
Data_X data inputs do not get written as the FIFO_DC is full (the Full flag is high).
Note that the assertion of these flags is immediate and there is no latency when they go true.
Now let us look at the waveforms when the contents of the FIFO_DC are read out. Figure 10-32 shows the start of
the read cycle. RdEn goes high and the data read starts. The Full and Almost Full flags are de-asserted, as shown.
In this case, note that the de-assertion is delayed by two clock cycles.
RPReset
WrClock
RdClock
Almost
Almost
Empty
Empty
Reset
WrEn
RdEn
Data
Full
Full
Q
Data_N-2
Data_N-1
10-30
Invalid Q
Data_N
Data_X
LatticeXP2 Memory Usage Guide
Data_X
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