LFXP2-30E-5FN484C Lattice, LFXP2-30E-5FN484C Datasheet - Page 326
![FPGA - Field Programmable Gate Array 30KLUTs 363 I/O Inst -on DSP 1.2V -5 Spd](/photos/16/15/161505/landingpagelatticexp2_sml.jpg)
LFXP2-30E-5FN484C
Manufacturer Part Number
LFXP2-30E-5FN484C
Description
FPGA - Field Programmable Gate Array 30KLUTs 363 I/O Inst -on DSP 1.2V -5 Spd
Manufacturer
Lattice
Specifications of LFXP2-30E-5FN484C
Number Of Macrocells
29000
Number Of Programmable I/os
363
Data Ram Size
396288
Supply Voltage (max)
1.26 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.14 V
Package / Case
FPBGA-484
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LFXP2-30E-5FN484C
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
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Lattice Semiconductor
Figure 18. LatticeXP2 Datasheet Note
3.
Reason: The JTAG port is designed to be all powerful so that even the PROGRAMN pin is disabled to pre-
vent the pin from interrupting the JTAG port operations.
Work-around Solution: Use the JTAG Refresh instruction to reboot instead of toggling the PROGRAMN
pin.
When the standard security fuse is set, use Background Mode to reprogram the LatticeXP2 device will fail
verification.
Reason: The function of the standard security fuse is for disabling the read back operation. Whenever
powering up the LatticeXP2 device, the security latch latches in the security fuse state to protect the fuse
pattern residing in it. The Background Mode programming by design can not alter or corrupt the current
pattern residing in the SRAM fuse module including the security latches. In other word, the security latch
can’t be cleared by Background operations. As a consequence, the security latch will block all subsequent
Background read back operation.
Work-around Solutions:
A. Skip verification on Background Mode programming.
B. Use Encryption Background Programming.
17-8
LatticeXP2 Dual Boot Feature
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