LFXP2-30E-5FN484C Lattice, LFXP2-30E-5FN484C Datasheet - Page 143

• Manufacturer Part Number: LFXP2-30E-5FN484C
• Description: FPGA - Field Programmable Gate Array 30KLUTs 363 I/O Inst -on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-30E-5FN484C

• Number Of Macrocells: 29000
• Number Of Programmable I/os: 363
• Data Ram Size: 396288
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 9-20. Timing Diagrams by DCS MODE (Cont.)
DCS Usage with VHDL - Example
COMPONENT DCS
-- synthesis translate_off
-- synthesis translate_on
END COMPONENT;
begin
DCSInst0: DCS
-- synthesis translate_off
attribute DCSMODE : string;
attribute DCSMODE of DCSinst0 : label is “POS”;
DCSOUT
DCSOUT
SEL
SEL
CLK1
CLK1
GENERIC
PORT
GENERIC MAP (
- Switch low @CLK1 falling edge.
- If SEL is low, output stays low at on
- Switch high @CLK1 rising edge.
- If SEL is low, output stays low high
CLK1 rising edge. SEL must not
change during setup prior to rising clock.
on CLK1 falling edge.
DCS MODE = HIGH_HIGH
DCS MODE = HIGH_LOW
(
DCSMODE : string :=
;
(
“POS”
9-21
DCSOUT
DCSOUT
SEL
SEL
CLK0
CLK0
- Switch low @CLK0 falling edge.
- If SEL is high, output stays low at
- Switch high @ CLK0 rising edge.
- If SEL is high, output stays high on
on CLK0 rising edge.
CLK0 falling edge.
DCS MODE = LOW_HIGH
DCS MODE = LOW_LOW
LatticeXP2 sysCLOCK PLL
Design and Usage Guide