LFXP2-30E-5FN484C Lattice, LFXP2-30E-5FN484C Datasheet - Page 270

• Manufacturer Part Number: LFXP2-30E-5FN484C
• Description: FPGA - Field Programmable Gate Array 30KLUTs 363 I/O Inst -on DSP 1.2V -5 Spd
• Manufacturer: Lattice

Specifications of LFXP2-30E-5FN484C

• Number Of Macrocells: 29000
• Number Of Programmable I/os: 363
• Data Ram Size: 396288
• Supply Voltage (max): 1.26 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.14 V
• Package / Case: FPBGA-484
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 13-12. MAC18X18MACB Packed into a sysDSP Block
sysDSP Blocks in the Report File
To check the configuration of the sysDSP Blocks in your design you can look at the MAP and Post PAR report files.
The MAP report file shows the mapped sysDSP components/primitives in your design. The Post PAR report file
shows the number of components in each sysDSP Block. The report files that follow show how the inferred MAC
was used.
MAP Report File
. MULT18X18MACB
Multiplier
Operation
Operation Registers
--------------------------------------------
Operation Registers
--------------------------------------------
SLOAD DATA1[15:0]*
SLOAD DATA3[15:0]*
MUI18A0[17:0]
MUI18B0[17:0]
MUI18A1[17:0]
MUI18B1[17:0]
MUI18A2[17:0]
MUI18B2[17:0]
MUI18A3[8:0]
MUI18B3[8:0]
Input
Pipeline
Input
Pipeline
addout_17_0:
SRIA[17:0]*
SRIB[17:0]*
SROA[17:0]*
SROB[17:0]*
Notes:
*These signals are optional.
**At least one clock is required.
Unsigned
CLK
CLK
18x18 - 0
18x18 - 1
18x18 - 2
18x18 - 3
CE
CE
CLK[3:0]**
RST[3:0]*
CE[3:0]*
13-11
RST
RST
unused
+/-
+/-
Lattice XP2 sysDSP Usage Guide
SOURCEA[3,1]*
SOURCEB[3,1]*
ADDNSUB[3,1]*
ACCUMSLOAD[3,1]*
SIGNEDA[3,1]*
SIGNEDB[3,1]*
Reg
Reg
Reg
Reg
Out
Out
Out
Out
0
1
2
3
OVERFLOW1
ACCUM1[51:0]
OVERFLOW3
ACCUM3[51:0]