ISL6323EVAL1Z Intersil, ISL6323EVAL1Z Datasheet - Page 14

• Manufacturer Part Number: ISL6323EVAL1Z
• Description: EVAL BOARD 1 FOR ISL6323
• Manufacturer: Intersil

Specifications of ISL6323EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

.
The effective internal R
current sensing process because it sets the gain of the load
line regulation loop when droop is enabled as well as the
gain of the channel-current balance loop and the overcurrent
trip level. The effective internal R
programmable and is set through use of the RSET pin.
Placing a single resistor, R
VCC pin programs the effective internal R
according to Equation 10.
The North Bridge regulator samples the load current in the
same manner as the Core regulator does. The R
will program all the effective internal R
same value.
Channel-Current Balance
One important benefit of multiphase operation is the thermal
advantage gained by distributing the dissipated heat over
multiple devices and greater area. By doing this the designer
avoids the complexity of driving parallel MOSFETs and the
expense of using expensive heat sinks and exotic magnetic
materials.
In order to realize the thermal advantage, it is important that
each channel in a multiphase converter be controlled to
carry about the same amount of current at any load level. To
achieve this, the currents through each channel must be
sampled every switching cycle. The sampled currents, I
from each active channel are summed together and divided
by the number of active channels. The resulting cycle
average current, I
current demand on the converter during each switching
cycle. Channel-current balance is achieved by comparing
the sampled current of each channel to the cycle average
current, and making the proper adjustment to each channel
pulse width based on the error. Intersil’s patented current
balance method is illustrated in Figure 6, with error
NOTE: Channel 3 and 4 are optional.
V
I
R
SEN
COMP
FIGURE 6. CHANNEL-1 PWM FUNCTION AND CURRENT-
ISEN
FILTER
=
=
I
L
--------- - R
400
⋅
3
----------------- -
R
+
I
DCR
ER
ISEN
BALANCE ADJUSTMENT
-
+
⋅
f(s)
I
1
SET
AVG
-
I
AVG
, provides a measure of the total load
ISEN
MODULATOR
WAVEFORM
÷ N
RAMP
SET
resistance is important to the
14
, from the RSET pin to the
ISEN
Σ
+
-
ISEN
resistance is user
PWM1
ISEN
resistors to the
I
I
I
4
3
2
resistance
SET
CONTROL
TO GATE
resistor
(EQ. 10)
LOGIC
(EQ. 9)
n
,
ISL6323
correction for Channel 1 represented. In the figure, the cycle
average current, I
sample, I
The filtered error signal modifies the pulse width
commanded by V
I
correction is applied to each active channel.
VID Interface
The ISL6323 supports hybrid power control of AMD
processors which operate from either a 6-bit parallel VID
interface (PVI) or a serial VID interface (SVI). The VID1/SEL
pin is used to command the ISL6323 into either the PVI
mode or the SVI mode. Whenever the EN pin is held LOW,
both the multiphase Core and single-phase North Bridge
Regulators are disabled and the ISL6323 is continuously
sampling voltage on the VID1/SEL pin. When the EN pin is
toggled HIGH, the status of the VID1/SEL pin will latch the
ISL6323 into either PVI or SVI mode. This latching occurs on
the rising edge of the EN signal.If the VID1/SEL pin is held
LOW during the latch, the ISL6323 will be placed into SVI
mode. If the VID1/SEL pin is held HIGH during the latch, the
ISL6323 will be placed into PVI mode. For the ISL6323 to
properly enter into either mode, the level on the VID1/SEL
pin must be stable no less that 1µs prior to the EN signal
transitioning from low to high.
6-Bit Parallel VID Interface (PVI)
With the ISL6323 in PVI mode, the single-phase North
Bridge regulator is disabled. Only the multiphase controller is
active in PVI mode to support uniplane VDD only
processors. Table 1 shows the 6-bit parallel VID codes and
the corresponding reference voltage.
ER
VID5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
toward zero. The same method for error signal
1
VID4
, to create an error signal I
TABLE 1. 6-BIT PARALLEL VID CODES
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
COMP
AVG
VID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
, is compared with the Channel 1
to correct any unbalance and force
VID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
VID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
ER
.
VID0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
October 21, 2008
1.5500
1.5250
1.5000
1.4750
1.4500
1.4250
1.4000
1.3750
1.3500
1.3250
1.3000
1.2750
1.2500
1.2250
1.2000
1.1750
VREF
FN9278.4