ISL6323EVAL1Z Intersil, ISL6323EVAL1Z Datasheet - Page 20

• Manufacturer Part Number: ISL6323EVAL1Z
• Description: EVAL BOARD 1 FOR ISL6323
• Manufacturer: Intersil

Specifications of ISL6323EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

During turn-off of the lower MOSFET, the PHASE voltage is
monitored until it reaches a -0.3V/+0.8V (forward/reverse
inductor current). At this time the UGATE is released to rise. An
auto-zero comparator is used to correct the r
phase voltage preventing false detection of the -0.3V phase
level during r
current, the UGATE is released after 35ns delay of the LGATE
dropping below 0.5V. When LGATE first begins to transition
low, this quick transition can disturb the PHASE node and
cause a false trip, so there is 20ns of blanking time once
LGATE falls until PHASE is monitored.
Once the PHASE is high, the advanced adaptive
shoot-through circuitry monitors the PHASE and UGATE
voltages during a PWM falling edge and the subsequent
UGATE turn-off. If either the UGATE falls to less than 1.75V
above the PHASE or the PHASE falls to less than +0.8V, the
LGATE is released to turn-on.
Initialization
Prior to initialization, proper conditions must exist on the EN,
VCC, PVCC1_2, PVCC_NB, ISEN3-, and ISEN4- pins. When
the conditions are met, the controller begins soft-start. Once
the output voltage is within the proper window of operation,
the controller asserts VDDPWRGD.
Power-On Reset
The ISL6323 requires VCC, PVCC1_2, and PVCC_NB
inputs to exceed their rising POR thresholds before the
ISL6323 has sufficient bias to guarantee proper operation.
FIGURE 12. POWER SEQUENCING USING THRESHOLD-
FAULT LOGIC
CIRCUIT
SOFT-START
POR
AND
ISL6323 INTERNAL CIRCUIT
DS(ON)
SENSITIVE ENABLE (EN) FUNCTION
conduction period. In the case of zero
CHANNEL
DETECT
ENABLE
COMPARATOR
20
+
-
V
EN_THR
PVCC1_2
EN
ISEN3-
VCC
PVCC_NB
ISEN4-
DS(ON)
EXTERNAL CIRCUIT
10.7kΩ
1.00kΩ
drop in the
+12V
ISL6323
The bias voltage applied to VCC must reach the internal
power-on reset (POR) rising threshold. Once this threshold
is reached, the ISL6323 has enough bias to begin checking
the driver POR inputs, EN, and channel detect portions of
the initialization cycle. Hysteresis between the rising and
falling thresholds assure the ISL6323 will not advertently
turn off unless the bias voltage drops substantially (see
“Electrical Specifications” on page 6).
The bias voltage applied to the PVCC1_2 and PVCC_NB
pins power the internal MOSFET drivers of each output
channel. In order for the ISL6323 to begin operation, both
PVCC inputs must exceed their POR rising threshold to
guarantee proper operation of the internal drivers.
Hysteresis between the rising and falling thresholds assure
that once enabled, the ISL6323 will not inadvertently turn off
unless the PVCC bias voltage drops substantially (see
“Electrical Specifications” on page 6). Depending on the
number of active CORE channels determined by the Phase
Detect block, the external driver POR checking is supported
by the Enable Comparator.
Enable Comparator
The ISL6323 features a dual function enable input (EN) for
enabling the controller and power sequencing between the
controller and external drivers or another voltage rail. The
enable comparator holds the ISL6323 in shutdown until the
voltage at EN rises above 0.86V. The enable comparator has
about 110mV of hysteresis to prevent bounce. It is important
that the driver ICs reach their rising POR level before the
ISL6323 becomes enabled. The schematic in Figure 12
demonstrates sequencing the ISL6323 with the ISL66xx
family of Intersil MOSFET drivers, which require 12V bias.
When selecting the value of the resistor divider the driver
maximum rising POR threshold should be used for
calculating the proper resistor values. This will prevent
improper sequencing events from creating false trips during
soft-start.
If the controller is configured for 2-phase CORE operation,
then the resistor divider can be used for sequencing the
controller with another voltage rail. The resistor divider to EN
should be selected using a similar approach as the previous
driver discussion.
The EN pin is also used to force the ISL6323 into either PVI
or SVI mode. The mode is set upon the rising edge of the EN
signal. When the voltage on the EN pin rises above 0.86V,
the mode will be set depending upon the status of the
VID1/SEL pin.
Phase Detection
The ISEN3- and ISEN4- pins are monitored prior to soft-start
to determine the number of active CORE channel phases.
If ISEN4- is tied to VCC, the controller will configure the
channel firing order and timing for 3-phase operation. If
ISEN3- and ISEN4- are tied to VCC, the controller will set
October 21, 2008
FN9278.4