ISL6323EVAL1Z Intersil, ISL6323EVAL1Z Datasheet - Page 18

• Manufacturer Part Number: ISL6323EVAL1Z
• Description: EVAL BOARD 1 FOR ISL6323
• Manufacturer: Intersil

Specifications of ISL6323EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Load-Line (Droop) Regulation
By adding a well controlled output impedance, the output
voltage can effectively be level shifted in a direction which
works to achieve a cost-effective solution can help to reduce
the output-voltage spike that results from fast load-current
demand changes.
The magnitude of the spike is dictated by the ESR and ESL
of the output capacitors selected. By positioning the no-load
voltage level near the upper specification limit, a larger
negative spike can be sustained without crossing the lower
limit. By adding a well controlled output impedance, the
output voltage under load can effectively be level shifted
down so that a larger positive spike can be sustained without
crossing the upper specification limit.
As shown in Figure 8, with the FS resistor tied to ground, the
average current of all active channels, I
through a load-line regulation resistor R
voltage drop across R
effectively creating an output voltage droop with a steady-
state value defined as in Equation 12:
The regulated output voltage is reduced by the droop voltage
V
shown in Equation 13.
V
DROOP
V
DROOP
FIGURE 8. OUTPUT VOLTAGE AND LOAD-LINE
OUT
+
-
R
C
R
FB
C
C
. The output voltage as a function of load current is
EXTERNAL CIRCUIT
(V
=
+
-
DROOP
I
AVG
R
REGULATION WITH OFFSET ADJUSTMENT
FS
⋅
+ V
R
FB
OFS
COMP
RGND
FB
VSEN
FB
)
FS
is proportional to the output current,
18
ISL6323 INTERNAL CIRCUIT
CONTROL
DROOP
∑
+
+
AVG
FB
+
-
. The resulting
, flows from FB
AMPLIFIER
I
I
ERROR
AVG
OFS
OSCILLATOR
DAC
VID
TO
(EQ. 12)
V
COMP
ISL6323
.
Where, V
programmed offset voltage, I
of the converter, K is the DC gain of the RC filter across the
inductor (K is defined in Equation 7), N is the number of
active channels, and DCR is the Inductor DCR value.
Output-Voltage Offset Programming
The ISL6323 allows the designer to accurately adjust the
offset voltage by connecting a resistor, R
pin to VCC or GND. When R
and VCC, the voltage across it is regulated to 1.6V. This
causes a proportional current (I
and out of the OFS pin. If R
voltage across it is regulated to 0.3V, and I
OFS pin and out of the FB pin. The offset current flowing
through the resistor between VDIFF and FB will generate the
desired offset voltage which is equal to the product
(I
and 10.
Once the desired output offset voltage has been determined,
use Equations 14 and 15 to set R
For Positive Offset (connect R
For Negative Offset (connect R
V
R
R
OFS
V
R
OUT
OFS
OFS
OFS
OFS
FIGURE 9. NEGATIVE OFFSET OUTPUT VOLTAGE
+
-
VDIFF
VCC
x R
=
=
=
I
OFS
R
V
0.3 R
--------------------------
V
1.6 R
--------------------------
V
REF
FB
FB
OFS
OFFSET
OFFSET
REF
FB
). These functions are shown in Figures 9
×
×
PROGRAMMING
is the reference voltage, V
–
FB
FB
V
ISL6323
OFS
–
VREF
⎛
⎜
⎝
I
------------ - DCR
OUT
N
OFS
OFS
OUT
⋅
OFS
OFS
OFS
is connected to ground, the
is connected between OFS
OFS
is the total output current
to GND):
) to flow into the FB pin
⋅
to VCC):
⎛
⎝
:
400
--------- -
+
-
3
+
-
OFS
OFS
E/A
GND
⋅
OFS
-------------- -
R
+
-
SET
+
1
, from the OFS
-
is the
0.3V
flows into the
⎞ K R
⎠
October 21, 2008
⋅
VCC
⋅
(EQ. 13)
(EQ. 14)
(EQ. 15)
FN9278.4
+
-
FB
1.6V
⎞
⎟
⎠