ISL6323EVAL1Z Intersil, ISL6323EVAL1Z Datasheet - Page 24

• Manufacturer Part Number: ISL6323EVAL1Z
• Description: EVAL BOARD 1 FOR ISL6323
• Manufacturer: Intersil

Specifications of ISL6323EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

all, there are some pin connections that must be made in
order for the ISL6323 to function properly. The ISEN_NB+
(pin 2) and ISEN_NB- (pin 47) pins as well as the RGND_NB
pin (pin 3) must be tied to ground. A small trace from the pin
to the ground pad under the part is all that is required. The
PVCC_NB pin (pin 42) should be tied to either +5V or to
+12V with a samll decoupling capacitor to ground. All other
pins associated with the North Bridge regulator may be left
unconnected.
General Design Guide
This design guide is intended to provide a high-level
explanation of the steps necessary to create a multiphase
power converter. It is assumed that the reader is familiar with
many of the basic skills and techniques referenced in the
following. In addition to this guide, Intersil provides complete
reference designs that include schematics, bills of materials,
and example board layouts for all common microprocessor
applications.
Power Stages
The first step in designing a multiphase converter is to
determine the number of phases. This determination
depends heavily on the cost analysis which in turn depends
on system constraints that differ from one design to the next.
Principally, the designer will be concerned with whether
components can be mounted on both sides of the circuit
board, whether through-hole components are permitted, the
total board space available for power-supply circuitry, and
the maximum amount of load current. Generally speaking,
the most economical solutions are those in which each
phase handles between 25A and 30A. All surface-mount
designs will tend toward the lower end of this current range.
If through-hole MOSFETs and inductors can be used, higher
per-phase currents are possible. In cases where board
space is the limiting constraint, current can be pushed as
high as 40A per phase, but these designs require heat sinks
and forced air to cool the MOSFETs, inductors and heat
dissipating surfaces.
MOSFETS
The choice of MOSFETs depends on the current each
MOSFET will be required to conduct, the switching frequency,
the capability of the MOSFETs to dissipate heat, and the
availability and nature of heat sinking and air flow.
LOWER MOSFET POWER CALCULATION
The calculation for power loss in the lower MOSFET is
simple, since virtually all of the loss in the lower MOSFET is
due to current conducted through the channel resistance
(r
output current, I
Equation 2), and d is the duty cycle (V
P
DS(ON)
LOW 1
,
). In Equation 21, I
=
r
DS ON
(
P-P
)
⋅
is the peak-to-peak inductor current (see
⎛
⎜
⎝
I
----- -
N
M
⎞
⎟
⎠
2
⋅
M
(
1 d
24
is the maximum continuous
–
)
+
I
------------------------------------------ -
L P-P
(
OUT
)
2
12
/V
⋅
(
IN
1 d
).
–
)
(EQ. 21)
ISL6323
An additional term can be added to the lower-MOSFET loss
equation to account for additional loss accrued during the
dead time when inductor current is flowing through the
lower-MOSFET body diode. This term is dependent on the
diode forward voltage at I
frequency, f
the beginning and the end of the lower-MOSFET conduction
interval respectively.
The total maximum power dissipated in each lower MOSFET
is approximated by the summation of P
UPPER MOSFET POWER CALCULATION
In addition to r
MOSFET losses are due to currents conducted across the
input voltage (V
higher portion of the upper-MOSFET losses are dependent
on switching frequency, the power calculation is more
complex. Upper MOSFET losses can be divided into
separate components involving the upper-MOSFET
switching times, the lower-MOSFET body-diode reverse
recovery charge, Q
conduction loss.
When the upper MOSFET turns off, the lower MOSFET does
not conduct any portion of the inductor current until the
voltage at the phase node falls below ground. Once the
lower MOSFET begins conducting, the current in the upper
MOSFET falls to zero as the current in the lower MOSFET
ramps up to assume the full inductor current. In Equation 23,
the required time for this commutation is t
approximated associated power loss is P
At turn-on, the upper MOSFET begins to conduct and this
transition occurs over a time t
approximate power loss is P
A third component involves the lower MOSFET
reverse-recovery charge, Q
fully commutated to the upper MOSFET before the
lower-MOSFET body diode can recover all of Q
conducted through the upper MOSFET across VIN. The
power dissipated as a result is P
Equation 25.
P
P
P
P
LOW 2
UP 1 ( )
UP 2 ( )
UP 3 ( )
,
≈
≈
=
=
V
V
V
IN
IN
V
IN
S
D ON
⋅
⋅
, and the length of dead times, t
(
⎛
⎝
⎛
⎜
⎝
⋅
DS(ON)
I
----- -
I
----- -
Q
N
N
M
M
IN
rr
)
+
–
⋅
) during switching. Since a substantially
⋅
f
I
--------- -
I
--------- -
S
rr
P-P
f
P-P
2
S
2
, and the upper MOSFET r
⋅
losses, a large portion of the upper
⎞
⎟
⎠
⎞
⎠
⎛
⎜
⎝
I M
------
⋅
N
⋅
⎛
⎜
⎝
M
⎛
⎜
⎝
+
t
----
t
----
2
2
2
, V
1
rr
I P-P
-----------
⎞
⎟
⎠
⎞
⎟
⎠
UP(2)
2
. Since the inductor current has
⋅
2
D(ON)
⋅
f
. In Equation 24, the
⎞
⎟
⎠
f
S
S
⋅
UP(3)
.
t d1
, the switching
+
as shown in
⎛
⎜
⎜
⎝
LOW,1
I M
------
N
UP(1)
1
–
I
-----------
and the
P-P
2
d1
and P
.
⎞
⎟
⎟
⎠
DS(ON)
and t
rr
⋅
October 21, 2008
, it is
t d2
LOW,2
d2
(EQ. 23)
(EQ. 22)
(EQ. 24)
(EQ. 25)
FN9278.4
, at
.