ISL6323EVAL1Z Intersil, ISL6323EVAL1Z Datasheet - Page 16

• Manufacturer Part Number: ISL6323EVAL1Z
• Description: EVAL BOARD 1 FOR ISL6323
• Manufacturer: Intersil

Specifications of ISL6323EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PRE-PWROK METAL VID
Typical motherboard start-up occurs with the VFIXEN input
low. The controller decodes the SVC and SVD inputs to
determine the Pre-PWROK metal VID setting. Once the
POR circuitry is satisfied, the ISL6323 begins decoding the
inputs per Table 2. Once the EN input exceeds the rising
enable threshold, the ISL6323 saves the Pre-PWROK metal
VID value in an on-board holding register and passes this
target to the internal DAC circuitry.
The Pre-PWROK metal VID code is decoded and latched on
the rising edge of the enable signal. Once enabled, the
ISL6323 passes the Pre-PWROK metal VID code on to
internal DAC circuitry. The internal DAC circuitry begins to
ramp both the VDD and VDDNB planes to the decoded
Pre-PWROK metal VID output level. The digital soft-start
circuitry actually stair steps the internal reference to the
target gradually over a fix interval. The controlled ramp of
both output voltage planes reduces in-rush current during
the soft-start interval. At the end of the soft-start interval, the
VDDPWRGD output transitions high indicating both output
planes are within regulation limits.
If the EN input falls below the enable falling threshold, the
ISL6323 ramps the internal reference voltage down to near
zero. The VDDPWRGD de-asserts with the loss of enable.
The VDD and VDDNB planes will linearly decrease to near
zero.
VFIX MODE
In VFIX Mode, the SVC, SVD and VFIXEN inputs are fixed
external to the controller through jumpers to either GND or
VDDIO. These inputs are not expected to change, but the
ISL6323 is designed to support the potential change of state
of these inputs. If VFIXEN is high, the IC decodes the SVC
and SVD states per Table 3.
Once enabled, the ISL6323 begins to soft-start both VDD
and VDDNB planes to the programmed VFIX level. The
000_0000b
000_0001b
000_0010b
000_0011b
000_0100b
000_0101b
SVID[6:0]
SVC
0
0
1
1
TABLE 2. PRE-PWROK METAL VID CODES
1.5500
1.5375
1.5250
1.5125
1.5000
1.4875
VOLTAGE (V)
SVD
0
1
0
1
16
010_0000b
010_0001b
010_0010b
010_0011b
010_0100b
010_0101b
OUTPUT VOLTAGE (V)
SVID[6:0]
1.1
1.0
0.9
0.8
1.1500
1.1375
1.1250
1.1125
1.1000
1.0875
TABLE 4. SERIAL VID CODES
VOLTAGE (V)
ISL6323
100_0000b
100_0001b
100_0010b
100_0011b
100_0100b
100_0101b
SVID[6:0]
internal soft-start circuitry slowly stair steps the reference up
to the target value and this results in a controlled ramp of the
power planes. Once soft-start has ended and both output
planes are within regulation limits, the VDDPWRGD pin
transitions high. If the EN input falls below the enable falling
threshold, then the controller ramps both VDD and VDDNB
down to near zero.
SVI MODE
Once the controller has successfully soft-started and
VDDPWRGD transitions high, the Northbridge SVI interface
can assert PWROK to signal the ISL6323 to prepare for SVI
commands. The controller actively monitors the SVI
interface for set VID commands to move the plane voltages
to start-up VID values. Details of the SVI Bus protocol are
provided in the AMD Design Guide for Voltage Regulator
Controllers Accepting Serial VID Codes specification.
Once the set VID command is received, the ISL6323
decodes the information to determine which plane and the
VID target required. See Table 4. The internal DAC circuitry
steps the required output plane voltage to the new VID level.
During this time one or both of the planes could be targeted.
In the event the core voltage plane, VDD, is commanded to
power off by serial VID commands, the VDDPWRGD signal
remains asserted. The Northbridge voltage plane must
remain active during this time.
If the PWROK input is de-asserted, then the controller steps
both VDD and VDDNB planes back to the stored
Pre-PWROK metal VID level in the holding register from
initial soft-start. No attempt is made to read the SVC and
SVD inputs during this time. If PWROK is reasserted, then
the on-board SVI interface waits for a set VID command.
If VDDPWRGD deasserts during normal operation, both
voltage planes are powered down in a controlled fashion.
The internal DAC circuitry stair steps both outputs down to
near zero.
SVC
0
0
1
1
0.7500
0.7375
0.7250
0.7125
0.7000
0.6875
VOLTAGE (V)
TABLE 3. VFIXEN VID CODES
SVD
0
1
0
1
110_0000b
110_0001b
110_0010b
110_0011b
110_0100b
110_0101b
SVID[6:0]
OUTPUT VOLTAGE (V)
1.4
1.2
1.0
0.8
0.3500*
0.3375*
0.3250*
0.3125*
0.3000*
0.2875*
VOLTAGE (V)
October 21, 2008
FN9278.4