ISL6323EVAL1Z Intersil, ISL6323EVAL1Z Datasheet - Page 21

• Manufacturer Part Number: ISL6323EVAL1Z
• Description: EVAL BOARD 1 FOR ISL6323
• Manufacturer: Intersil

Specifications of ISL6323EVAL1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the channel firing order and timing for 2-phase operation
(see “PWM Operation” on page 12 for details). If Channel 4
and/or Channel 3 are disabled, then the corresponding
PWMn and ISENn+ pins may be left unconnected.
Soft-Start Output Voltage Targets
Once the POR and Phase Detect blocks and enable
comparator are satisfied, the controller will begin the
soft-start sequence and will ramp the CORE and NB output
voltages up to the SVI interface designated target level if the
controller is set SVI mode. If set to PVI mode, the North
Bridge regulator is disabled and the core is soft started to the
level designated by the parallel VID code.
SVI MODE
Prior to soft-starting both CORE and NB outputs, the
ISL6323 must check the state of the SVI interface inputs to
determine the correct target voltages for both outputs. When
the controller is enabled, the state of the VFIXEN, SVD and
SVC inputs are checked and the target output voltages set
for both CORE and NB outputs are set by the DAC (see
“Serial VID Interface (SVI)” on page 15). These targets will
only change if the EN signal is pulled low or after a POR
reset of VCC.
Soft-Start
The soft-start sequence is composed of three periods, as
shown in Figure 13. At the beginning of soft-start, the DAC
immediately obtains the output voltage targets for both
outputs by decoding the state of the SVI or PVI inputs. A
100µs fixed delay time, TDA, proceeds the output voltage
rise. After this delay period the ISL6323 will begin ramping
both CORE and NB output voltages to the programmed DAC
level at a fixed rate of 3.25mV/µs. The amount of time
required to ramp the output voltage to the final DAC voltage
is referred to as TDB, and can be calculated as shown in
Equation 19.
After the DAC voltage reaches the final VID setting,
VDDPWRGD will be set to high.
TDB
=
----------------------------- -
3.25
V
DAC
×
10
–
3
21
(EQ. 19)
ISL6323
.
Pre-Biased Soft-Start
The ISL6323 also has the ability to start up into a
pre-charged output, without causing any unnecessary
disturbance. The FB pin is monitored during soft-start, and
should it be higher than the equivalent internal ramping
reference voltage, the output drives hold both MOSFETs off.
Once the internal ramping reference exceeds the FB pin
potential, the output drives are enabled, allowing the output to
ramp from the pre-charged level to the final level dictated by
the DAC setting. Should the output be pre-charged to a level
exceeding the DAC setting, the output drives are enabled at
the end of the soft-start period, leading to an abrupt correction
in the output voltage down to the DAC-set level.
Both CORE and NB output support start up into a
pre-charged output.
FIGURE 14. SOFT-START WAVEFORMS FOR ISL6323-BASED
OUTPUT PRECHARGED
BELOW DAC LEVEL
5V/DIV
FIGURE 13. SOFT-START WAVEFORMS
EN
OUTPUT PRECHARGED
MULTIPHASE CONVERTER
ABOVE DAC LEVEL
TDA
400mV/DIV
5V/DIV
V
EN
NB
100µs/DIV
VDDPWRGD
100µs/DIV
TDB
5V/DIV
400mV/DIV
V
CORE
400mV/DIV
V
October 21, 2008
CORE
FN9278.4