NRF9E5 NORDIC SEMICONDUCTOR, NRF9E5 Datasheet - Page 38

• Manufacturer Part Number: NRF9E5
• Description: TRX, 430-928MHZ, MCU/ADC/PWM, SMD
• Manufacturer: NORDIC SEMICONDUCTOR

Specifications of NRF9E5

• Receiving Current: 12.5mA
• Transmitting Current: 30mA
• Data Rate: 50Kbps
• Frequency Range: 430MHz To 928MHz
• Modulation Type: GFSK
• Rf Ic Case Style: QFN
• No. Of Pins: 32
• Supply Voltage Range: 1.9V To
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PRODUCT SPECIFICATION
nRF9E5 Single Chip Transceiver with Embedded Microcontroller and ADC
11.4 RF – Configuration Register Description
Main office: Nordic Semiconductor ASA - Vestre Rosten 81, N-7075 Tiller, Norway -Phone [phone] - Fax [phone]
Revision: 1.3
Parameter
ADDRESS
RX_RED_
UP_CLK_
RX_AFW
TX_AFW
PA_PWR
RETRAN
HFREQ_
CRC_EN
DIRECT
CH_NO
RX_PW
TX_PW
AUTO_
MODE
FREQ
CRC_
PWR
XO_
XOF
RX_
PLL
Bitwidth
32
9
1
2
1
1
3
3
6
6
2
1
3
1
1
Table 22 RF configuration-register description.
Description
Sets center frequency together with HFREQ_PLL (default value = 001101100
Sets PLL in 433 or 868/915 MHz mode (default value = 0).
Output power (default value = 00).
Reduces current in RX mode by 1.6mA. Sensitivity is reduced (default value = 0).
Retransmit contents in TX – register as long TRX_CE and TXEN is high (default value = 0).
RX-address width (default value = 100).
TX-address width (default value = 100).
RX-payload width (default value = 100000).
TX-payload width (default value = 100000).
RX address identity. Used bytes depend on RX_AFW (default value = E7E7E7E7
CPU clock frequency (default value = 00).
CPU clock select (default value = 0).
Crystal oscillator frequency. Must be set according to external crystal resonant-frequency.
CRC – check enable (default value = 1).
CRC – mode (default value = 1).
'0' – Chip operating in 433MHz band
'1' – Chip operating in 868 or 915 MHz band
'00' -10dBm
'01' -2dBm
'10' +6dBm
'11' +10dBm
'0' – Normal operation
'1' – Reduced power
'0' – No retransmission
'1' – Retransmission of data packet
'001' – 1 byte RX address field width
'100' – 4 byte RX address field width
'001' – 1 byte TX address field width
'100' – 4 byte TX address field width
'000001' – 1 byte RX payload field width
'000010' – 2 byte RX payload field width
'100000' – 32 byte RX payload field width
'000001' – 1 byte TX payload field width
'000010' – 2 byte TX payload field width
'100000' – 32 byte TX payload field width
'00' – 4MHz
'01' – 2MHz
'10' – 1MHz
'11' – 500kHz
'0' – CPU using UP_CLK_FREQ frequency
'1' – CPU using XOF frequency
'000' – 4MHz
'001' – 8MHz
'010' – 12MHz
'011' – 16MHz
'100' – 20MHz
'0' – Disable
'1' – Enable
'0' – 8 CRC check bit
'1' – 16 CRC check bit
f
RF
.
.
.
.
= ( 422.4 + CH_NO
Page 38 of 108
d
/10)*(1+HFREQ_PLL
(SFR 0xBF have to correspond with UP_CLK_FREQ)
(default value = Set by boot-loader to the same
(SFR 0xBF have to correspond with XOF).
value as XO_FREQ[2:0] from the EEPROM-
header (see Table 53, p.62))
d
) MHz
(SFR 0xBF have to correspond
with XO_DIRECT)
June 2006
b
= 108
h
).
d
).